No abstract

A 15-bit 125-MS/s two-channel time-interleaved Channel 1 pipelined ADC is fabricated in a 0.18 ,um CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. CHP1 X_ Stage 1 Stage 2-Bit The ADC uses a single sample-and-hold amplifier which employs 1 _ 17 _Flash a precharging circuit technique to mitigate the performance Dl D17 D18 1 requirements for its opamp. Digital background calibration is

Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.

A 15-bit 125-MS/s two-channel time-interleaved Channel 1 pipelined ADC is fabricated in a 0.18 ,um CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. CHP1 X_ Stage 1 Stage 2-Bit The ADC uses a single sample-and-hold amplifier which employs 1 _ 17 _Flash a precharging circuit technique to mitigate the performance Dl D17 D18 1 requirements for its opamp. Digital background calibration is

Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies.the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology construct$d by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overaIl improvement o f the system throughput is 20% for 844 test cases. ASP-DAC 2005