Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Lin, Liang‐Yu; Wang, Cheng-Yeh; Huang, Pao-Jui; Chou, Chih-Chieh; Jou, Jing-Yang

doi:10.1145/1120725.1120739

Cited by 17 publications

(5 citation statements)

References 22 publications

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“…The majority of existing application mapping methodologies fall into the category of static approaches, see, for example, References [29][30][31][32][33]. In these approaches, all mapping decisions are made offline.…”

Section: Related Workmentioning

confidence: 99%

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

Pourmohseni

Glaß

Henkel

et al. 2020

JLPEA

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Many-core platforms are rapidly expanding in various embedded areas as they provide the scalable computational power required to meet the ever-growing performance demands of embedded applications and systems. However, the huge design space of possible task mappings, the unpredictable workload dynamism, and the numerous non-functional requirements of applications in terms of timing, reliability, safety, and so forth. impose significant challenges when designing many-core systems. Hybrid Application Mapping (HAM) is an emerging class of design methodologies for many-core systems which address these challenges via an incremental (per-application) mapping scheme: The mapping process is divided into (i) a design-time Design Space Exploration (DSE) step per application to obtain a set of high-quality mapping options and (ii) a run-time system management step in which applications are launched dynamically (on demand) using the precomputed mappings. This paper provides an overview of HAM and the design methodologies developed in line with it. We introduce the basics of HAM and elaborate on the way it addresses the major challenges of application mapping in many-core systems. We provide an overview of the main challenges encountered when employing HAM and survey a collection of state-of-the-art techniques and methodologies proposed to address these challenges. We finally present an overview of open topics and challenges in HAM, provide a summary of emerging trends for addressing them particularly using machine learning, and outline possible future directions. While there exists a large body of HAM methodologies, the techniques studied in this paper are developed, to a large extent, within the scope of invasive computing. Invasive computing introduces resource awareness into applications and employs explicit resource reservation to enable incremental application mapping and dynamic system management.

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Section: Related Workmentioning

confidence: 99%

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

Pourmohseni

Glaß

Henkel

et al. 2020

JLPEA

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“…More recent work in homogeneous design time partitioning of streaming applications can be found in Gordon [2], Lin [9], Kudlur and Mahlke [10], Wei [11], and Wang [12].…”

Section: R E L At E D W O R Kmentioning

confidence: 99%

“…Lin et al [9] use simulated annealing to build a communication driven task binding algorithm. The partitioner attempts to reduce communication resource usage by estimating communication cost based on Manhattan distances between nodes.…”

Section: R E L At E D W O R Kmentioning

confidence: 99%

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC

Kelly

Flasskamp

Sievers

et al. 2014

2014 International Symposium on System-on-Chip (SoC)

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Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulatedannealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%. I . I N T R O D U C T I O NThe decreasing feature size of microelectronic circuits allows for the integration of more and more processing cores on a single chip. A Multiprocessor System-on-Chip (MPSoC) may consist of dozens of processing elements as CPU cores or specialized hardware accelerators connected by a highspeed communication infrastructure, i.e. a Network-On-Chip (NoC). However, mapping general purpose applications to a large number of MPSoC processing elements remains a nontrivial task. Manually writing low-level code for each core makes it difficult to experiment with different decompositions and mappings of computation to processors. Alternatively, higher-level programming frameworks allow the compiler to evaluate a larger design-space when mapping the application to different hardware configurations. Efficient mapping algorithms are important for finding optimized solutions. The Streaming paradigm provides regular and repeating computation and independent filters with explicit communication. This allows compilers to exploit the task more easily, data and pipeline parallelism commonly found in signal processing, multimedia, network processing, cryptology and similar application domains.A popular stream based programming language is StreamIt [1], [2]. The key principle of this language is to provide information about inherent parallelism of the program by using a structured data flow graph. This graph consisting of filters, pipelines, split-joins, and feedback loops.In this paper we present a compiler for the StreamIt Language targeting the self-build CoreVA-MPSoC architecture. The CoreVA-MPSoC is a highly scalable multiprocessor system based on a hierarchical communication infrastructure and the configurable VLIW 1 processor CoreVA.This paper is organized as follows: Section II describes our CoreVA-MPSoC hardware architecture. In Section III we discuss our StreamIt compiler with a focus on our novel simulated annealing partitioning algorithm (Smart SA). The communication model proposed in this work is presented in S...

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“…[23] gives a nice survey of the existing mapping methodologies. In the context of static mapping performance optimization, some classic algorithms such as Simulated Annealing (SA) [18], [14], Genetic Algorithm (GA) [6], [1], [19], Tabu Search [15] and Integer Linear Programming (ILP) [9] have been proposed. Among these algorithms, the GA is considered to be a good mapping algorithm because it can obtain a good result in a short time period [4].…”

Section: Sensitivity To Beg Implementation Choicesmentioning

confidence: 99%

Exploring Task Mappings on Heterogeneous MPSoCs using a Bias-Elitist Genetic Algorithm

Quan,

Pimentel

2014

Preprint

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Exploration of task mappings plays a crucial role in achieving high performance in heterogeneous multi-processor system-on-chip (MPSoC) platforms. The problem of optimally mapping a set of tasks onto a set of given heterogeneous processors for maximal throughput has been known, in general, to be NP-complete. The problem is further exacerbated when multiple applications (i.e., bigger task sets) and the communication between tasks are also considered. Previous research has shown that Genetic Algorithms (GA) typically are a good choice to solve this problem when the solution space is relatively small. However, when the size of the problem space increases, classic genetic algorithms still suffer from the problem of long evolution times. To address this problem, this paper proposes a novel bias-elitist genetic algorithm that is guided by domain-specific heuristics to speed up the evolution process. Experimental results reveal that our proposed algorithm is able to handle large scale task mapping problems and produces high-quality mapping solutions in only a short time period.

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Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Cited by 17 publications

References 22 publications

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC

Exploring Task Mappings on Heterogeneous MPSoCs using a Bias-Elitist Genetic Algorithm

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