Hybrid Wordlength Optimization Methods of Pipelined FFT Processors

Word-length optimization of a pipelined FFT processor

“…Another effective data scaling approach for pipelined FFT processor is hybrid floating point [1][2] [3]. Compared to CBFP, hybrid floating point does not need intermediate buffer to hold common scaling factor, and every data in each stage has its own exponent which means data can be scaled dynamically.…”

“…The concept block diagram of simulation based analysis is shown as Fig.4. From the Matlab models, fixed-point and hybrid floating point performance results can be obtained, and then SQNR can be evaluated by comparing fixed-point or hybrid floating results with floating point results, the SQNR calculation formula is as follow [1]. In hybrid floating point processor, the input data is not formatted as hybrid floating point in the first radix-2 stage.…”

“…When implementing FFT algorithm in ASIC, the internal word-length and data formats are important, they will affect both performance and complexity [1][2] [3]. The precision of the results is dependent on the data format and word-length, when the internal data word-length is longer or the data is formatted as floating point, the number is represented more precisely.…”

A dynamic scaling length-variable FFT processor

“…[ ] x n [ 8 ] x n N + [ 4 ] x n N + [ 3 8] x n N + [ 2 ] x n N + [ 5 8] x n N + [ 3 4] x n N + The radix-2/4/8 algorithm can implement radix-8 butterfly with three radix-2 butterfly. The radix-2/4/8 architecture is shown as Fig.…”

“…Figure. 3 Architecture of FFT Processor III. WORDLENGTH OPTIMIZATION One important issue designing pipelined FFT processor is the wordlength in the architecture, which will affect precision and number of gates [4]. In fixed-point FFT, the internal wordlength is often increased with one bit in each addition operation to maintain data accuracy and achieve higher SQNR.…”