A dynamic scaling length-variable FFT processor

He, Jing; Xu, Xinyu

doi:10.1109/cisp.2010.5647304

Cited by 2 publications

(3 citation statements)

References 8 publications

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“…Figure.2b SDF architecture of radix-2/4/8 unit To perform 8192 point FFT, mixed radix algorithm is adopted which mixes radix-2 and radix-2/4/8 DIF algorithm. One stage of radix-2 computation unit and four stages of radix-8 computation units are cascaded [7]. The 8192 point FFT processor architecture is shown in Fig.3.…”

Section: Pipelined Fft Architecturementioning

confidence: 99%

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Word-length optimization of a pipelined FFT processor

Wang

2011

2011 International Conference on Consumer Electronics, Communications and Networks (CECNet)

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In this paper, word-length optimization for a pipelined 8K FFT processor is presented. The processor is based on radix-2/4/8 and mixed radix algorithm, and SDF architecture is used. The internal word-length and data format are important issues when designing pipelined FFT processors, it will affect precision and gate number. To obtain a good solution, three Matlab models for the processor are developed in which the internal data are formatted as floating point, fixed point and hybrid floating point respectively, and simulations are performed. The simulation results show that hybrid floating point can achieve better and constant performance compared to fixed point with progressive word-length in term of SQNR and memory size.

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Section: Pipelined Fft Architecturementioning

confidence: 99%

“…Efficient implementation of FFT is essential for OFDM systems, and is also a challenge due to the requirement of high throughput and high accuracy [4][5] [7].…”

Section: Introductionmentioning

confidence: 99%

Word-length optimization of a pipelined FFT processor

Wang

2011

2011 International Conference on Consumer Electronics, Communications and Networks (CECNet)

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“…A variable-length FFT processor design is based on a radix-2/4/8 algorithm and single path delay feedback architecture is reported [1][2]. To meet flexibility of FFT size, [3]presented an architecture that base on radix-2,radix-2 2 and radix-2/4/8 algorithms. [4][5]propose radix-2 2 architecture based on R2 2 SDF.…”

Section: Introductionmentioning

confidence: 99%

A Variable-Length FFT Processor Base on Mixed-Radix Algorithm for PAPR Reduction in OFDM Systems

Meng

Wang

Yan

2012

AMR

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An attractive technique of variable-length Fast Fourier transform (FFT) processor is proposed for PAPR reduction in orthogonal frequency division multiplexing (OFDM) systems. Mixed-radix algorithm and single path delay feedback (SDF) pipeline architecture is adopted to obtain low computation complexity and preferable flexibility for its VLSI implementation. The FFT processor can be reconfigured as 512, 1024, 2048, 4096-points, moreover, the only one RAM unit is used for store sine/cosine tables. The chip is mapped to the 0.18 CMOS technology and the core area is 7.896mm2. The experiment results show that the proposed FFT processor is suitable for PAPR reduction in OFDM communication systems.

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A dynamic scaling length-variable FFT processor

Cited by 2 publications

References 8 publications

Word-length optimization of a pipelined FFT processor

Word-length optimization of a pipelined FFT processor

A Variable-Length FFT Processor Base on Mixed-Radix Algorithm for PAPR Reduction in OFDM Systems

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