A 15-bit 125-MS/s two-channel time-interleaved Channel 1 pipelined ADC is fabricated in a 0.18 ,um CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. CHP1 X_ Stage 1 Stage 2-Bit The ADC uses a single sample-and-hold amplifier which employs 1 _ 17 _Flash a precharging circuit technique to mitigate the performance Dl D17 D18 1 requirements for its opamp. Digital background calibration is
A 15-bit 125-MS/s two-channel time-interleaved Channel 1 pipelined ADC is fabricated in a 0.18 ,um CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. CHP1 X_ Stage 1 Stage 2-Bit The ADC uses a single sample-and-hold amplifier which employs 1 _ 17 _Flash a precharging circuit technique to mitigate the performance Dl D17 D18 1 requirements for its opamp. Digital background calibration is
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