A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration

Lee, Zwei-Mei; Wang, Cheng-Yeh; Wu, Jieh-Tsorng

doi:10.1109/cicc.2006.320912

Cited by 9 publications

(9 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several methods have been introduced that minimize the offset and gain mismatch for time-interleaved ADCs [3], [4]. However, timing offset is the most critical for multi-gigahertz multi-phase operation, as these timing offsets result in ADC sampling errors and therefore a reduction in ADC resolution.…”

Section: A Previous Methods For Time-interleaved Calibrationmentioning

confidence: 99%

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

Xia

Wang

Beattie

et al. 2012

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

A foreground digital calibration method is presented that calibrates the timing offsets between the multiple T/H (track/hold) circuits of time-interleaved analog-to-digital converters and multi-phase serial links. Two quantizer-based phase detectors sample the outputs of adjacent track/hold circuits, detecting any phase offsets arising from process mismatches in both the timing verniers and the T/H switches, and store the resulting digital decisions in histogram counters. Measurement inaccuracies resulting from quantizer offset are averaged away statistically by a round-robin rotation of the dual samplers, compensating for comparator imprecision. Built in a 90-nm CMOS process, the proposed calibration technique, after three iterations of both the phase measurement and subsequent timing vernier adjustment, reduces the static phase offset of each channel to less than 0 5 ps in an 8-channel, 8 GS/s time-interleaved system. Further measurements using a T/H circuit as a down-conversionmixer confirm a residual phase error of less than 2 ps.

show abstract

Section: A Previous Methods For Time-interleaved Calibrationmentioning

confidence: 99%

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

Xia

Wang

Beattie

et al. 2012

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…None of these calibration algorithms takes into account the nonlinear errors of the constituent channels, that have to be corrected separately (see for example [15], [16] ) with techniques such as [9] or [17], at the expense of design complexity and, possibly, convergence time. Moreover, it has to be noted that the technique used to estimate and calibrate the timing mismatches sets a limit on the fraction of the Nyquist bandwidth that can be effectively exploited by the TI-ADC.…”

Section: Introductionmentioning

confidence: 99%

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

Centurelli

Monsurrò

Trifiletti

2012

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band

show abstract

“…1). A single front-rank sample-and-hold amplifier (SHA) can be used to avoid sample-time error [1]. However, this method limits the overall speed of TI ADCs because of the bottleneck on the performance and power efficiency of the front-rank SHA.…”

mentioning

confidence: 99%

Mixed-signal calibration of sample-time error in time-interleaved ADCs

Zhang

et al. 2011

Electron. Lett.

View full text Add to dashboard Cite

A mixed-signal scheme is presented to calibrate sample-time error in time-interleaved (TI) analogue-to-digital converters (ADCs). Based on the information collected by the timing error detection subsystem through digital processing, sample-time error is corrected using the proposed voltage-controlled bootstrapped switch. A two-channel TI-ADC system of 14-bit 200 MS/s has been implemented to evaluate the performance of the technique. Simulation results show that the ADC system achieves a 77.4 dB SNDR and an 84.3 dB SFDR at 97.7 MHz after calibration.Introduction: A recent trend in wideband wireless communication systems is to sample IF and even RF signals with ADCs directly. This requirement imposes a design challenge on high-speed and high-resolution ADCs. Such an ADC can be achieved with a time-interleaved architecture in which multiple identical sub-ADC cores are integrated. However, the performance of time-interleaved (TI) ADCs is limited by non-idealities such as mismatches of offsets, gains, bandwidths, and sample-time error among the sub-ADCs' channel (shown in Fig. 1). A single front-rank sample-and-hold amplifier (SHA) can be used to avoid sample-time error [1]. However, this method limits the overall speed of TI ADCs because of the bottleneck on the performance and power efficiency of the front-rank SHA. Another way to deal with sample-time error is calibration. Calibration of sample-time error consists of a detection subsystem and a correction one. Generally, error detection is performed in the digital domain either in the foreground [2] or the background [3]. As for the error correction, there are two schemes. The first is a digital correction with complex digital signal processing techniques, such as blind calibration [4]. The alternative is an analogue correction, by tuning the clock-path delay with a digitally controlled delay element (DCDE) [5], which will increase the random jitter of the sampling clock.

show abstract

A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration

Cited by 9 publications

References 14 publications

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

Mixed-signal calibration of sample-time error in time-interleaved ADCs

Contact Info

Product

Resources

About