In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this increase is due to the 3-D nature of the device and also due to the close proximity of the source/drain (S/D) epitaxial (epi) region to the metal gate. Using well-calibrated 3-D mixed-mode simulations, we show that this will cause the performance of FinFETs to be significantly degraded, unless proper device optimizations are carried out. Our results also indicate that the selective epi growth of S/D may adversely affect the overall performance of FinFETs, although it is effective in reducing series resistance. The increased parasitic components in FinFETs can be a serious issue for FinFET circuits with a large fan-out, and the solution lies in the aggressive fin pitch reduction, as shown in this letter.
Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(0) shaped slruchue, at a conservative 17-19 A gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 pNpm and 780 pA/pm with off state leakage currents of 8 n N p and 0.4 nNpm for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 p A / p for N-FET and 550 pNpm for P-FET at an off current of 1 pNpm. N-FET gate delay (CYII) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections [I].
This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.Index Terms-CMOS, coulomb blockade oscillation, multiple gate, silicon-on-insulator (SOI), single-electron effect, single-electron transistor.
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