25 nm CMOS Omega FETs

Yang, Fu-Liang; Chen, Haoyu; Chen, Fang-Cheng; Huang, Chien-Yao; Chang, Chang-Yun; Chiu, H. C.; Lee, Chi-Chuang; Chen, Chi‐Chun; Huang, Huan-Tsung; Chen, Chih-Jian; Tao, Hun-Jan; Yeo, Yee-Chia; Liang, Mong–Song; Hu, Chenming

doi:10.1109/iedm.2002.1175826

Cited by 68 publications

(7 citation statements)

References 3 publications

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“…It can be easily obtained by a slight overetching of the buried oxide during the Si island patterning. The gate extension improves the control of the channel by the gate and thereby lowers the role of short-channel effects [16,18,[114][115][116]. As can be seen from Fig.…”

Section: An Advanced Approach For Mosfet Downsizing In Nanometer Regionmentioning

confidence: 85%

The advancement of silicon-on-insulator (SOI) devices and their basic properties

Rudenko¹,

Nazarov²,

Lysenko³

2020

SPQEO

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Silicon-on-insulator (SOI) is most promising present-day silicon technology. The use of SOI provides significant benefits over traditional bulk silicon technology in fabrication of many integrated circuits (ICs), and in particular, complementary metal-oxidesemiconductor (CMOS) ICs. It also allows extending the miniaturization of CMOS devices into the nanometer region. In this review paper, we briefly describe evolution of SOI technology and its main areas of application. The basic technological methods for fabrication of SOI wafers are presented. The principal advantages of SOI devices over bulk silicon devices are described. The types of SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) and their basic electrical properties are considered.

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Section: An Advanced Approach For Mosfet Downsizing In Nanometer Regionmentioning

confidence: 85%

The advancement of silicon-on-insulator (SOI) devices and their basic properties

Rudenko¹,

Nazarov²,

Lysenko³

2020

SPQEO

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“…In 1999, Huang et al [8] demonstrated the first FinFET with a gate length L G of sub-50 nm and a fin width of 15− 30 nm. Following that, leading research groups and foundries like IBM [11] , STMicroelectronics [15] , Intel [5,10] , TSMC [16,27] , Samsung [17] . IME [18] , etc.…”

Section: Process Development Of Si Multi-gate Transistors 21 a Histor...mentioning

confidence: 99%

“…(a-f) Schematics of MuGFETs with different gate geometries: (a) IMEC's gate-all-around (GAA) MOSFET [14] , (b) the world-first FinFET [8] , (c) IBM's double-gate (DG) FinFET [11] , (d) STMicroelectronics's GAA MOSFET [15] , (e) Intel's tri-gate FinFET [10] , (f) TSMC's nanowire FinFET [16] . (g-i) TEM images showing the cross-sectional view of fins/nanowires from early works: (g) IBM's DG FinFET [11] , (h) Intel's tri-gate FinFET [10] , (i) Samsung's nanowire MOSFET [17] , (j) IME's nanowire GAA MOSFET [18] , (k) TSMC's FinFET [27] , (l) STMicroelectronics's GAA MOSFET [28] . ferent process technology, namely, bulk planar FETs, fully-depleted SOI (FDSOI) FETs, and FinFETs [29] .…”

Section: Process Development Of Si Multi-gate Transistors 21 a Histor...mentioning

confidence: 99%

“…However, since the architecture for planar SOI MOSFETs with front and back gate is not suitable for back-end of line (BEOL) design, vertically in-parallel double gate structures has been realized on SOI MOS-FETs, which is the early structural prototype for multi-gate MOSFET devices [7] . Later on, multi-gate transistors, namely, double-gate (DG) FinFET [8,9] , tri-gate FinFET [5,10,11] , Ω-gate MOSFETs [12] , segmented-gate (SG) MOSFETs [13] , gate-allaround (GAA) MOSFETs [14,15] , 3D stacked nanowire (NW) MOS-FETs [16−18] , multilayer nanosheet MOSFETs [19] , were immensely studied and massively demonstrated, especially after its compatibility with the conventional Si CMOS platform was demonstrated by UCBerkeley [8] . Excellent gate control and mobility improvement could be achieved by the realization of volume inversion especially for structures with more degree of gate wrapping and smaller cross-sectional channel area normal to the carrier transport direction.…”

Section: Introductionmentioning

confidence: 99%

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The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Sun

Zhang

et al. 2021

J. Semicond.

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This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

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“…Source-to-drain quantum tunnelling [7]- [9] or variability [10]- [12] is much more pronounced and deteriorate the I ON /I OFF ratio in current ultrascaled devices. To overcome this problem, a variety of new architectures, including ultrathin silicon-on-insulator (SOI) [13]- [15], double gate [13], [16], FinFETs [17], [18], trigate [19], -gate [20], junctionless (JL) [21], and gate all-around nanowire FETs [22], have therefore been developed to improve the electrostatic control of the conducting channel. In those architectures, the surface surrounded by the gate is increased in relation to the channel volume, improving the electrostatic control.…”

Section: Impact Of Randomly Distributed Dopants Onmentioning

confidence: 99%

Impact of Randomly Distributed Dopants on $\Omega$ -Gate Junctionless Silicon Nanowire Transistors

Carrillo-Nuñez

Mirza

Paul

et al. 2018

IEEE Trans. Electron Devices

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This paper presents experimental and simulation analysis of an -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on driftdiffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean I D -V Gs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean I D -V Gs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs.Index Terms-Drift diffusion (DD), electronic transport, junctionless (JL) nanowire field-effect transistors (FETs) (JL-NWTs), random dopants, scattering mechanisms, silicon nanowire, simulations, variability.

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25 nm CMOS Omega FETs

Cited by 68 publications

References 3 publications

The advancement of silicon-on-insulator (SOI) devices and their basic properties

The advancement of silicon-on-insulator (SOI) devices and their basic properties

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Impact of Randomly Distributed Dopants on $\Omega$ -Gate Junctionless Silicon Nanowire Transistors

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