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Understanding the consequences of local surface charging on the evolving etching profile is a critical challenge in high density plasma etching. Deflection of the positively charged ions in locally varying electric fields can cause profile defects such as notching, bowing, and microtrenching. We have developed a numerical simulation model capturing the influence of the charging effect over the entire course of the etching process. The model is fully integrated into ViPER (Virtual Plasma Etch Reactor)—a full featured plasma processing simulation software developed at Ilmenau University of Technology. As a consequence, we show that local surface charge concurrently evolves with the feature profile to affect the final shape of the etched feature. Using gas chopping (sometimes called time-multiplexed) etch process for experimental validation of the simulation, we show that the model provides excellent fits to the experimental data and both, bowing and notching effects are captured—as long as the evolving profile and surface charge are simultaneously simulated. In addition, this new model explains that surface scallops, characteristic of gas chopping technique, are eroded and often absent in the final feature profile due to surface charging. The model is general and can be applied across many etching chemistries.

Articles you may be interested inSelf-sensing cantilevers with integrated conductive coaxial tips for high-resolution electrical scanning probe metrology All-diamond cantilever probes for scanning probe microscopy applications realized by a proximity lithography process Rev. Sci. Instrum. 77, 043708 (2006); Scanning proximity probes are uniquely powerful tools for analysis, manipulation, and bottom-up synthesis. A massively parallel cantilever-probe platform is demonstrated. 128 self-sensing and self-actuated proximal probes are discussed. Readout based on piezoresistive sensors and bending control based on bimorph dc/ac actuations are described in detail.

In the last years, silicon micromachining techniques based on high aspect ratio reactive ion etching with gas chopping have been developed. There the gas flow of etching and deposition gas precursors is chopped which results in controllable sidewall passivation and high anisotropy. However, the rippled sidewalls are a serious limit for various applications. We report on the development of a novel gas chopping etching technique (GCET) process in order to achieve a smooth (rippled free) sidewall surface. As the direct etch mask, we used a 1 or 2-μm-thick resist layer, which was lithographically patterned. The novelty of the process consists in the replacing of the isotropic etching step by an anisotropic etching step. In this way we omit the main source for sidewall ripples. GCET combined with inductively coupled plasmas and fluorine chemistry provide very high etch rates and good control of the sidewall slope. These techniques also can be applied to conventional reactive ion etching equipment with Cl or F based plasma chemistry. However, the techniques used in this study have lower selectivity (in range of 30) than the conventional GCET. A SiON/Si selectivity as high as 50 has been achieved.

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Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

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Articles you may be interested inProfile simulation model for sub-50 nm cryogenic etching of silicon using S F 6 / O 2 inductively coupled plasma J. Appl. Phys. 118, 053302 (2015); 10.1063/1.4927731Finite-element simulation models and experimental verification for through-silicon-via etching: Bosch process and single-step etching