A near-infrared (NIR) enhanced silicon single-photon avalanche diode (SPAD) fabricated in a customized 0.13 µm CMOS technology is presented. The SPAD has a depleted absorption volume of approximately 15 µm × 15 µm × 18 µm. Electrons generated in the absorption region are efficiently transported by drift to a central active avalanche region with a diameter of 2 µm. At the operating voltage, the active region contains a spherically uniform field peak, enabling the multiplication of electrons originating from all corners of the device. The advantages of the SPAD architecture include high NIR photon detection efficiency (PDE), drift-based transport, low afterpulsing, and compatibility with an integrated CMOS readout. A front-side illuminated device is fabricated and characterized. The SPAD has a PDE of 13% at wavelength 905 nm, an afterpulsing probability < 0.1% for a dead time of 13 ns, and a median dark count rate (DCR) of 840 Hz at room temperature. The device shows promising performance for time-of-flight applications that benefit from uniform NIR-sensitive SPAD arrays.

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This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−.