Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

Abstract

This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e−.

Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor

“…As mentioned previously, high-speed CMOS image sensors are prone to relatively high noise due to the trade-off between design requirements for fast readout speed and lower thermal noise. In order to tackle this issue, a passive correlated double sampling (CDS) amplifier was proposed by Wu et al [6] to reduce input-referred noise. However, the gain of the passive CDS amplifier relies on the capacitance ratio between the NMOS capacitor in depletion mode and inversion mode, which is dependent on both the process A TCAD transient simulation was conducted to verify the complete charge transfer of the proposed design.…”

“…and voltage. Consequently, this introduces an unavoidable non-linearity to the entire image sensor, approximately at a level of 3% [6]. Furthermore, the settling of the amplified voltage imposes limitations on the frame rate.…”

Direct Time-of-Flight Single-Photon Imaging

“…High speed burst-mode CCDs and CMOS image sensors integrate hundreds of taps with commensurately low fill-factor but are unable to integrate on-chip over successive illumination cycles. [7].…”

A pipeline row operation method of CMOS image sensors

“…Compared with charge coupled device (CCD), complementary metal oxide semiconductor (CMOS) image sensor has advantages of readout frame rate, cost, and power, which is now extensively used in consumer, surveillance, industrial applications. For scientific imaging, the image sensor needs to deliver high sensitivity [1,2], high frame rate [3,4,5,6,7,8,9] and low noise [10,11,12,13,14,15]. Scientific CMOS image sensors (sCMOS) can provide high sensitivity, high speed, and low noise simultaneously.…”