Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

and data-center networks 3, 6, 7

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

High quality factor (Q approximately 3.4 x 10(6)) microdisk resonators are demonstrated in a Si(3)N(4) on SiO(2) platform at 652-660 nm with integrated in-plane coupling waveguides. Critical coupling to several radial modes is demonstrated using a rib-like structure with a thin Si(3)N(4) layer at the air-substrate interface to improve the coupling.

High quality (Q approximately 6 x 10(5)) microdisk resonators are demonstrated in a Si(3)N(4) on SiO(2) platform at 652-660 nm with integrated in-plane wrap-around coupling waveguides to enable critical coupling to specific microdisk radial modes. Selective coupling to the first three radial modes with >20dB suppression of the other radial modes is achieved by controlling the wrap-around waveguide width. Advantages of such pulley-coupled microdisk resonators include single mode operation, ease of fabrication due to larger waveguide-resonator gaps, the possibility of resist reflow during the lithography phase to improve microdisk etched surface quality, and the ability to realize highly over-coupled microdisks suitable for low-loss delay lines and add-drop filters.

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The strong thermooptic effect in silicon enables low-power and low-loss reconfiguration of large-scale silicon photonics. Thermal reconfiguration through the integration of metallic microheaters has been one of the more widely used reconfiguration techniques in silicon photonics. In this paper, structural and material optimizations are carried out through heat transport modeling to improve the reconfiguration speed of such devices, and the results are experimentally verified. Around 4 micros reconfiguration time are shown for the optimized structures. Moreover, sub-microsecond reconfiguration time is experimentally demonstrated through the pulsed excitation of the microheaters. The limitation of this pulsed excitation scheme is also discussed through an accurate system-level model developed for the microheater response.

No abstract