Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited]

Abstract

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

“…To this end, a potential on-board layout of the 40 Gb/s C2C interconnect will probably eliminate the need for SOAs in the transmission lines, turning C2C energy consumption into a parameter that depends solely on the power requirements of the RM and its respective electronic driver, the PD-TIA and the external LD that feeds the RM with the CW optical beam. Considering the employment of state-ofthe-art RM drivers [138] and assuming an LD with 6.1 dBm output power and a 10% wall-plug efficiency, the energy efficiency of the proposed 40 Gb/s C2C photonic link was estimated at 5.95 pJ/bit that increases to 6.25 pJ/bit when incorporating also state-of-the-art SerDes [139] , assuming a LD-to-RM coupling loss of 3dB [140], a RM insertion loss of 1.5 dB, 0.5dB for every Silicon-to-polymer and polymer-to-Silicon waveguide coupling [131] and an AWGR channel insertion loss of 6dB [135]. These energy efficiency values suggest a 63.3% and 61.4% improvement, respectively, compared to the 16.2 pJ/bit link energy efficiency of Intel QPI [134].…”

Triply resonant coupled-cavity electro-optic modulators for RF to optical signal conversion

“…In particular, we are interested in realization of the proposed concept in advanced CMOS processes, such as "zero-change" monolithic electronic-photonic 45 nm CMOS [17]. Integration of silicon photonic devices and circuits in advanced RF CMOS processes (some having standard f T /f max of 305/380 GHz [18] and f T as high as 485 GHz [19]), in close proximity to RF-electronic circuits, bears potential for realization of large-scale, on-chip MWP systems, such as RF-optical beamforming networks for next generation mobile communication systems, satellite-based mm-wave sensors for atmospheric temperature sounding [4], etc.…”

Multi-Level Analysis of On-Chip Optical Wireless Links

“…Various viable solutions have been proposed in the literature for the inclusion of the optical layer in the chip stack. For example, the optical layer can be placed on-top of the electronic interconnection layers [27,28] as shown in Figure 1, or in plane with it [29][30][31]. The layer stack is finally completed by additional upper layers accounting for possible passivation/filling materials and for the outer package enclosure.…”