Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.

Abstract-Integrated photonic interconnects have emerged recently as a potential solution for relieving on-chip and chipto-chip bandwidth bottlenecks for next-generation many-core processors. To help bridge the gap between device and circuit/system designers, and aid in understanding of inherent photonic link tradeoffs, we present a set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology. To compensate for process and thermal-induced ring resonator mismatches, we take advantage of device and circuit characteristics to propose an efficient ring tuning solution. Finally, we perform optimization of a wavelength-division-multiplexed link, demonstrating the linklevel interactions between components in achieving the optimal degree of parallelism and energy-efficiency.

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We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects.

Abstract-A monolithically-integrated optical receiver for lowenergy on-chip and off-chip communication is presented. The monolithic photodiode integration enables the energy-efficient and high-sensitivity sense-amplifier-based receiver design. The receiver is characterized in situ and shown to operate with μA-sensitivity at 3.5 Gb/s with a power consumption of 180 μW (52 fJ/bit) and area of 108 μm 2 . This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.

Integrated photonic interconnect technology presents a disruptive alternative to electrical I/O for many VLSI applications. Superior bandwidth-density and energy-efficient operation can be realized through dense wavelength-division multiplexing (DWDM) and lower transmission losses. There are two main paths towards an integrated platform. Hybrid/heterogeneous designs [1][2][3] enable each component to be custom-tailored, but suffer from large packaging parasitics, increased manufacturing costs due to requisite process flows, and costly 3D integration or microbump packaging. Monolithic integration mitigates integration overheads, but has not penetrated deeply-scaled technologies due to necessary process customizations [4]. The first monolithic integration of photonic devices and electronic-photonic operation in sub-100 nm (45 nm SOI process with zero foundry changes) is demonstrated in [5]. This paper presents a monolithically integrated optical modulator with a new all-digital driver circuit in a commercial 45nm SOI process. The waveform-conditioning driver circuit enables the carrier-injection modulator to operate at 2.5Gb/s with an energy-cost of 1.23pJ/b, making it ~4× faster and more energy-efficient than the previous monolithically integrated driver/modulator presented in [5].The double-data-rate (DDR) modulator and driver circuit (Fig. 7.6.1) are fabricated as part of a 5M-transistor integrated platform for optical I/O. Light from an off-chip laser couples onto the die through vertical grating couplers and propagates through on-chip silicon waveguides. Fed by two 31b on-chip pseudo-random bit sequence (PRBS) generators, the DDR modulator circuit drives the modulator device to imprint data onto a particular wavelength-channel. A digital snapshot checks the validity of the generated data. The optically-modulated data is brought off-chip through a vertical grating coupler and measured using an optical oscilloscope.The optical modulator device is a resonant ring with rib waveguide carrier-injection phase shifters, identical to the one in [5], implemented using a combination of the gate polysilicon and body silicon layers in the process front-end. The device cross-section and transfer function are illustrated in Fig. 7.6.2. The optical 3dB bandwidth of the device is 45GHz. Modulation is achieved by tuning the ring in and out of the wavelength-channel through carrier injection. Due to long carrier lifetimes in single-crystalline Si, this device has an electrical 3dB bandwidth of approximately 250MHz that limits the data-rate in [5] to 600Mb/s at an energy cost of 4.2pJ/b. The driver we present in this work overcomes this bandwidth limitation through optimized drive conditioning with the same optical device design and 1950μm 2 area footprint.The DDR driver circuit (Fig. 7.6.3) is designed as an all-digital push-pull driver circuit with configurable drive strengths, sub-bit-time pre-emphasis [6] and split supplies, operating over a range of drive current profiles required for a wide variety of optical devices. The ...