Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

and data-center networks 3, 6, 7

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

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The effective transport properties of heterogeneous nanoscale materials and structures are affected by several geometrical and physical factors. Among them the presence of imperfect interfaces plays a central role being often at the origin of the scale effects. To describe real contacts between different phases some classical schemes have been introduced in literature, namely the low and the high conducting interface models. Here, we introduce a generalized formalism, which is able to take into account the properties of both previous schemes and, at the same time, it implements more complex behaviors, already observed in recent investigations. We apply our models to the calculation of the effective conductivity in a paradigmatic structure composed of a dispersion of particles. In particular we describe the conductivity dependence upon the size of the inclusions finding an unusual non-monotone scale effect with a pronounced peak at a given particle size. We introduce some intrinsic length scales governing the universal scaling laws.

Correlated photon pairs are a fundamental building block of quantum photonic systems. While pair sources have previously been integrated on silicon chips built using customized photonics manufacturing processes, these often take advantage of only a small fraction of the established techniques for microelectronics fabrication and have yet to be integrated in a process which also supports electronics. Here we report the first demonstration of quantumcorrelated photon pair generation in a device fabricated in an unmodified advanced (sub-100 nm) complementary metal-oxide-semiconductor (CMOS) process, alongside millions of working transistors. The microring resonator photon pair source is formed in the transistor layer structure, with the resonator core formed by the silicon layer typically used for the transistor body. With ultra-low continuous-wave on-chip pump powers ranging from 5 µW to 400 µW, we demonstrate pair generation rates between 165 Hz and 332 kHz using >80% efficient WSi superconducting nanowire single photon detectors. Coincidences-to-accidentals ratios consistently exceeding 40 were measured with a maximum of 55. In the process of characterizing this source we also accurately predict pair generation rates from the results of classical stimulated four-wave mixing measurements. This proof-of-principle device demonstrates the potential of commercial CMOS microelectronics as an advanced quantum photonics platform with capability of large volume, pristine process control, and where state-of-the-art high-speed digital circuits could interact with quantum photonic circuits.This manuscript describes work of the U.S. government and is not subject to copyright.