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For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming 123 234 S. Dikmese et al.accuracy, FPGA resource utilization, weight vector computation time, and DOA estimation error are presented. Beamformer weight vectors using LMS and CM can be computed within less than 20 µs on Virtex II FPGA and 10 µs on Virtex IV FPGA, and using SCC it can be achieved within less than 22 µs on Virtex IV FPGA. These results show that FPGAs provide approximately 500 times faster speed in implementations than our previous work with DSPs.

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Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP-and FPGA-based implementations of space-code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Du ¼ 28, whereas it can be achieved within less than 25 ms on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.