FPGA Based Implementation and Comparison of Beamformers for CDMA2000

Abstract

For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming 123 234 S. Dikmese et al.accuracy, FPGA resource utilization, weight vector computation time, and DOA estimation error are presented. Beamformer weight vectors using LMS and CM can be computed within less than 20 µs on Virtex II FPGA and 10 µs on Virtex IV FPGA, and using SCC it can be achieved within less than 22 µs on Virtex IV FPGA. These results show that FPGAs provide approximately 500 times faster speed in implementations than our previous work with DSPs.

Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas

“…In this paper, we extend our previous works [11][12][13] on DSP and FPGA implementations for wireless environments. We specifically focus on implementation of a smart antenna algorithm that we have developed earlier and referred to as space-code correlator algorithm (SCC) using TI floatingpoint DSP (C6713 DSK) [13] and Xilinx's VirtexIV FPGA. Signal received from the antenna array is assumed to be transmitted in CDMA2000 format [14].…”

“…The SCC algorithm whose implementation on DSP and FPGA to be presented in this paper was also discussed in [13,16]. It is based on performing code correlation with desired user's code and then spatial correlation of despread signal with predetermined array response vectors in the reverse link search table.…”

“…1. For the ease of understanding, we provide the explanation of implementation blocks as described in [13]. Implementation blocks on an FPGA are composed of six entities named as Main, Search Code correlator entity: Code correlator process is implemented for 64 complex multiplications (in multiplier entity, adder) and additions in total of n ¼ 60 steps.…”

A Pareto Elite Selection Genetic Algorithm for Random Antenna Array Beamforming With Low Sidelobe Level

“…The proposed PESGA's computational time is only slightly higher than the conventional GA method. For applications of the algorithm, a Graphic Processing Unit (GPU) or Field Programmable Gate Array (FPGA) can be used to make the algorithm execution much faster [30,36,37].…”

A Reconfigurable Smart Antenna Beamforming Architecture for Secure Localization Applications

“…Digital Signal Processor (DSP), General Purpose Microprocessor Unit (MPU), Application-Specific Integrated Circuits (ASICs) commonly exist in the literature. FPGA-based design technology is now best suited for a wireless sensor network infrastructure (Dikmese et al 2011). Since an adaptive array antenna system typically operates at a higher frequency (on the order of a few GHz), it needs a high-speed parallel processor to compute the array weight vector for such applications (Nuteson et al 2002).…”