Digital signal processor against field programmable gate array implementations of space–code correlator beamformer for smart antennas

Abstract

Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP-and FPGA-based implementations of space-code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Du ¼ 28, whereas it can be achieved within less than 25 ms on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.

A Reconfigurable Smart Antenna Beamforming Architecture for Secure Localization Applications

“…Also, its execution time is comparable to the others. (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.022 LMS (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.059 CM (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.091 MSR-CORDIC (Thiripurasundari et al 2017) Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.017 QRD-RLS (Dick et al 2006) Xilinx virtex 4 (XC4VLX60, 250 MHz) 0.057 D 3 (Jarrah and Jamali 2013) Xilinx Artix 7 (XA7A100T, 8.45 MHz) 6…”

“…It can handle arithmetic overflows and user-specified resource constraints. Dikmese et al 2010Dikmese et al , 2011 also presented a comparative study to verify the feasibility of implementing a beamforming architecture on DSP and FPGA. They envisioned floating-point implementations for some CDMA compatible beamforming algorithms, namely Least Mean Square (LMS), Constant Modulus (CM), and Space Code Correlator (SCC).…”

“…Since an adaptive array antenna system typically operates at a higher frequency (on the order of a few GHz), it needs a high-speed parallel processor to compute the array weight vector for such applications (Nuteson et al 2002). FPGA families can use their reconfigurable architectures to generate bundles of different shaped beams as needed from time to time in the data routing operation (Dikmese et al 2010). In addition, it can meet resource constraints requiring relatively minimal hardware.…”

A Study on Radar Target Detection using Space Time Adaptive Processing Algorithm and LCMV Algorithm

“…The adaptive array antenna system has an advantage of eliminating interference signals, minimizing noise power, and avoiding frequency dependent phase distortion on the spread width signal [6][7][8][9][10][11][12][13][14]. However, broadband requires temporary filtering of array signal processing to suppress interference signals.…”

FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO

“…At the same time in the designs implemented using FPGAs, by making changes easily, significant gains from time and cost are provided 2 . These properties, in addition to being used in many fields such as digital signal processing 3 , communication 4 , robotics 5 , is also preferred in the Artificial Neural Network applications 6,7,8 .…”