With the widespread use of battery operating systems, low power designs are highly needed to extend the battery lifetime. Encryption/ decryption circuits are one of the best candidates for low power implementation, as they are needed to maintain the privacy and security of user data. In this work, we present a low power FPGA-based implementation for AES Mix Columns (MC) /Inverse Mix Columns (IMC). The proposed design achieves low power by applying precomputation and resource sharing techniques to the MC and IMC transformation. We compared this implementation with previous work and we found that this implementation provides an average of 28% less power than previous implementations.
Cryptography techniques need some algorithms for encryption of data. Many of available encryption techniques are used for textual data, a few of encryption methods are used for multimedia data; however, this algorithms that are used for textual data may be inefficient for multimedia. The most popular symmetric key algorithms are Data Encryption Standard (DES). However, DES may not be suitable for multimedia because it consumes times. Encryption and decryption of these data require different methods. This paper proposes an encryption and decryption of data by using the nature of Fractional Fourier Transform (FrFT) in signals analysis, based on multi-order FrFT. A different indicators to evaluate the security of an encryption technique have been discussed. These indicators are: sensitivity proposed techniques for the key, the complexity of the processes, and statistical analysis. The key is formed by combination of order of FrFT. The encrypted data is obtained by the summation of different orders. Numerical simulation results are given to demonstrate this proposed method.
can be independently configured for a different standard. To maximize flexibility and performance, the chip is designed with leading edge general purpose and fixed function processing elements that are efficiently linked using a central switch and DMA. This SoC offers unprecedented signal processing performance by integrating 5,928Million C-programmable MACs/sec and 6,547Million configurable DSP-accelerator (DSPA) MACs/sec. The C-programmable elements were implemented using three DSP cores each running at 494MHz. The chip contains over 107 million transistors and is implemented in 0.13µm CMOS technology with 6-layer copper metallization. The full chip dissipates 2.7 W in ADSL2+ mode at room temperature.
In this paper, a VHDL synthesizable model for AutoLogic IT is developed for an unpipelined version of the 32-bit DLX RISC processor, called DLXS. The VNDL RTL model is synthesized, optimized, simulated, and laid out using Mentor Graphics EDA tools. The designed ASIC is based on the CMOSN standard cell library-with 0 . 8~ technology. The processor clock frequency is 33 MHz and the chip area is 8.7x9.2 mm'.
A new complete design and implementation of FPGA-based Three Dimensions CORDIC processor (3D-CORDIC)is introduced. Efficient mappings on FPGA have been performed leading to the fastest implementations. Simulation process have been performed for the proposed 3D-CORDIC processor using ModelSim SE tools of Mentor Graphics simulations and the MATLAB Software simulations, a good agreement of the proposed processor performance has been achieved. The 3D-CORDIC processor architecture has been implemented with 12 bit word-length in Xilinx Spartan-II series field programmable gates arrays (FPGA). The 3D-CORDIC processor use only 37 % of SLICEs and 52 % of IOBs with maximum clock frequency 116 MHz, which is suitable for many CORDIC processor applications.
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