Low Power Implementation of AES Mix Columns/ Inverse Mix Column on FPGA

Abstract

With the widespread use of battery operating systems, low power designs are highly needed to extend the battery lifetime. Encryption/ decryption circuits are one of the best candidates for low power implementation, as they are needed to maintain the privacy and security of user data. In this work, we present a low power FPGA-based implementation for AES Mix Columns (MC) /Inverse Mix Columns (IMC). The proposed design achieves low power by applying precomputation and resource sharing techniques to the MC and IMC transformation. We compared this implementation with previous work and we found that this implementation provides an average of 28% less power than previous implementations.

A modified MixColumn-InversMixColumn in AES algorithm suitable for hardware implementation using FPGA device

“…The implementation uses decomposition techniques, precomputation, and parallel power supply to reduce a power circuit. The circuit consumption is decreased as compared to previous implementations [13].…”

“…MixColumns/InverseMixColumns transforma-tion consumed more power and logic so that optimization is important [13]. In traditional AES, MixColumns and Inverse MixColumns are implemented as separate modules, except for some implementations which used sharing resource between MixColumns and Inverse MixColumns to optimize power and space [14], [15].…”