Synthesis and physical design of DLX RISC processor

Abstract

In this paper, a VHDL synthesizable model for AutoLogic IT is developed for an unpipelined version of the 32-bit DLX RISC processor, called DLXS. The VNDL RTL model is synthesized, optimized, simulated, and laid out using Mentor Graphics EDA tools. The designed ASIC is based on the CMOSN standard cell library-with 0 . 8~ technology. The processor clock frequency is 33 MHz and the chip area is 8.7x9.2 mm'.