A novel design and implementation of FPGA based 3D-CORDIC processor

Abstract

A new complete design and implementation of FPGA-based Three Dimensions CORDIC processor (3D-CORDIC)is introduced. Efficient mappings on FPGA have been performed leading to the fastest implementations. Simulation process have been performed for the proposed 3D-CORDIC processor using ModelSim SE tools of Mentor Graphics simulations and the MATLAB Software simulations, a good agreement of the proposed processor performance has been achieved. The 3D-CORDIC processor architecture has been implemented with 12 bit word-length in Xilinx Spartan-II series field programmable gates arrays (FPGA). The 3D-CORDIC processor use only 37 % of SLICEs and 52 % of IOBs with maximum clock frequency 116 MHz, which is suitable for many CORDIC processor applications.