This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.
Time-to-market pressure and increased design complexity created what is called a "design gap" [1] in the design of systems-on-chip (SoC). As a solution to that problem the Platform-Based Design (PBD), based on the design-reuse methodology, has been proposed [2], and successfully applied to digital systems. However, nowadays, the analog part of SoC does not take advantage of PBD and therefore dominates the overall design time, cost and risk. In this paper we propose a Mixed-signal FPGA (FPMA) platform as a solution to the problems described above. Specifically, we address the feasibility of a flexible reprogrammable/reconfigurable ADC platform based on the pipelined architecture. We discuss the programmability issues with respect to the performance-flexibility trade-offs, we justify our decisions and we demonstrate several possible ADC architectures.
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