A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

Doris, Kostas; Janssen, Éric; Nani, Claudio; Zanikopoulos, A.; Weide, G. van der

doi:10.1109/jssc.2011.2164961

Cited by 129 publications

(70 citation statements)

References 23 publications

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“…The CMOS bootstrapped switch is widely used for sampling in ADC due to its higher overdrive voltage and better linearity [1,2,3,4,5], compared to the non-bootstrapped switches. A classic bootstrapped switch is presented in [1].…”

Section: Introductionmentioning

confidence: 99%

“…To be more compact, another widely-used bootstrapped switch in [2] eliminates the charge pump, yet the bootstrap capacitor is still large to keep the overdrive loss small due to the gate parasitic capacitive load. The precharge technique [3,4] can greatly reduce the bootstrap capacitance, and increase the operating speed, but the input range is limited. In this paper, an improved scheme based on the precharge technique is proposed, which extends the input range to full swing without any sacrifice of area or speed.…”

Section: Introductionmentioning

confidence: 99%

“…A conclusion is provided in Section 5. The operation scheme of the precharge technique in [3,4] can be divided in three phases, precharge, track, and hold, as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…According to [3], C B can be 25% that of the conventional way. The downsized C B leads to decreased area, increased bootstrap bandwidth, and steep track rising transient [4].…”

Section: Introductionmentioning

confidence: 99%

“…Given the advantages in the precharge technique in [3,4] described above, however, there are two limitations that make this topology not suitable for rail-to-rail input. On the one hand, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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A full-swing area-efficient high-speed CMOS bootstrapped sampling switch

Zhou

2013

IEICE Electron. Express

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High performance bootstrapped switch is critical to high speed analog-to-digital converters (ADCs). This paper presents a novel CMOS bootstrapped switch which achieves rail-to-rail input range with greatly reduced bootstrap capacitance while maintaining high speed based on the precharge technique and charge leakage control. The proposed scheme is implemented in a 65 nm CMOS technology. Simulation results demonstrate that the proposed bootstrapped switch can achieve full-swing input range at 200 MHz Nyquist with a chip area of 25 µm by 20 µm.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…A conclusion is provided in Section 5. The operation scheme of the precharge technique in [3,4] can be divided in three phases, precharge, track, and hold, as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…According to [3], C B can be 25% that of the conventional way. The downsized C B leads to decreased area, increased bootstrap bandwidth, and steep track rising transient [4].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A full-swing area-efficient high-speed CMOS bootstrapped sampling switch

Zhou

2013

IEICE Electron. Express

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A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters

Navidi,

Navidi

2024

Circuit Theory & Apps

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A significant challenge in designing high‐speed time‐interleaved ADCs (TI‐ADCs) is the presence of time skew mismatch, resulting from uneven sampling across different channels and constituting a significant source of error. This error can be mitigated either by employing samplers unaffected by time skew or by employing foreground/background time skew calibration methods. Considering that the complexity of time skew calibration can complicate analog‐to‐digital converter (ADC) design, simpler techniques are essential, particularly with the development of higher‐speed ADCs using smaller technology nodes. This paper offers a comprehensive examination of various techniques applied in TI‐ADCs to address time skew‐related issues. We will explore skew‐tolerant sampling techniques to alleviate time skew errors, followed by an exploration of background time skew calibration methods. The primary focus of this paper centers on background time skew calibration techniques, which have become integral to improving the dynamic performance of high‐speed TI‐ADCs. The main background time skew calibration techniques to be reviewed include error injection techniques, reference ADC‐based techniques, input slope estimation, autocorrelation‐based techniques, and variance‐based techniques.

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Recent progress on CMOS successive approximation ADCs

Matsuura

2016

IEEJ Transactions Elec Engng

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Recent progress in CMOS integrated successive approximation (SAR) analog-to-digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non-necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time-interleaved architecture, it achieves a very high speed conversion rate of 90 G-sample/s with an 8-bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10-bit, 200 k-sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR-ADC circuit techniques and the achieved performances.

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A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS

Cited by 129 publications

References 23 publications

A full-swing area-efficient high-speed CMOS bootstrapped sampling switch

A full-swing area-efficient high-speed CMOS bootstrapped sampling switch

A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters

Recent progress on CMOS successive approximation ADCs

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