This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC-because the latter must wait for the settling time of the DAC inside the SAR ADC.
This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with novel non-binary DAC structure and digital correction techniques. All blocks are implemented in a single chip with 0.044mm 2 /0.066mm 2 for analog/logic. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0dB in GSM and 58.2dB in WCDMA/LTE are achieved at the sampling frequencies of 52MS/s and 80MS/s, respectively.
A 12-bit algorithmic (cyclic) ADC is designed and fabricated in 90nm CMOS, and only occupies as small active area as 0.037mm 2 . With the proposed radix-value self-estimation scheme for a non-binary 1-bit/step architecture, the accuracy requirement on analog components is largely relaxed. Therefore, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density MOM capacitors can be used to achieve small area. Furthermore, the novel radixvalue self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves 62.3dB SNDR at 1.4V power supply and 1.25Msps (20MHz clocking) using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz input.
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