An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components

Abstract

A 12-bit algorithmic (cyclic) ADC is designed and fabricated in 90nm CMOS, and only occupies as small active area as 0.037mm 2 . With the proposed radix-value self-estimation scheme for a non-binary 1-bit/step architecture, the accuracy requirement on analog components is largely relaxed. Therefore, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density MOM capacitors can be used to achieve small area. Furthermore, the novel radixvalue self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves 62.3dB SNDR at 1.4V power supply and 1.25Msps (20MHz clocking) using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz input.

A <I>&beta;</I>-ary to binary conversion for random number generation using a <I>&beta;</I> encoder

“…San et al have manufactured CMOS circuits in which β encoders are embedded [19][20][21]. The parameter β of the β encoder is designed to satisfy 1.7869 ≤ β ≤ 1.9000 [21].…”

“…Moreover, the effective β is estimated by a simple algorithm [12]. These characteristics of β encoder enable us to implement a β encoder in a very small CMOS circuit [19][20][21]. This is the main advantage of β encoder over 1.5 bit A/D converter.…”

“…Thus, a β encoder is robust to fluctuation of threshold value of a quantizer. Such a β encoder does not need high-precision circuit elements and is implemented by an electronic circuit that achieves very small area consumption as well as low power consumption [19][20][21][22]. A β encoder is composed of an amplifier with an amplification factor β and a comparator that outputs a digital code 0 or 1.…”

“…The differences between the proposed algorithm and the conventional algorithms [27,[29][30][31][32]] are 1. Coin random numbers are the outputs from a hardware β encoder [20,21]. The source of the randomness is the uncertainty in the initial state of the system.…”

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components

“…Because the large capacitors need more silicon areas, the active area of high-resolution SAR ADC becomes significantly larger than other ADC architectures. To resolve the design issues as described above, this paper presents an area-efficieny cyclic ADC which integrates a compact analog part for non-binary A-to-D conversion and a simple digital part for non-binary to binary encoding with selfestimated radix-value [3]. In our previous work, we have proposed an analog to non-binary digital converter structure with radix-value estimation algorithm, and demonstrated the analog area efficiency of non-binary architecture [4], [5].…”