A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters

Abstract

A significant challenge in designing high‐speed time‐interleaved ADCs (TI‐ADCs) is the presence of time skew mismatch, resulting from uneven sampling across different channels and constituting a significant source of error. This error can be mitigated either by employing samplers unaffected by time skew or by employing foreground/background time skew calibration methods. Considering that the complexity of time skew calibration can complicate analog‐to‐digital converter (ADC) design, simpler techniques are essential, particularly with the development of higher‐speed ADCs using smaller technology nodes. This paper offers a comprehensive examination of various techniques applied in TI‐ADCs to address time skew‐related issues. We will explore skew‐tolerant sampling techniques to alleviate time skew errors, followed by an exploration of background time skew calibration methods. The primary focus of this paper centers on background time skew calibration techniques, which have become integral to improving the dynamic performance of high‐speed TI‐ADCs. The main background time skew calibration techniques to be reviewed include error injection techniques, reference ADC‐based techniques, input slope estimation, autocorrelation‐based techniques, and variance‐based techniques.