An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

Janssen, Éric; Doris, Kostas; Zanikopoulos, A.; Murroni, Alessandro; Weide, G. van der; Lin, Yu Chang; Alvado, Ludovic; Darthenay, F.; Fregeais, Y.

doi:10.1109/isscc.2013.6487816

Cited by 64 publications

(55 citation statements)

References 2 publications

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“…The reconstruction can be performed either in the analog domain [22,23] or in the digital domain [24]. Analog reconstructors use the mismatch estimates to perform the correction in the analog domain.…”

Section: Chapter 1 Backgroundmentioning

confidence: 99%

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Pillai¹

2015

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An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TI-ADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs.iii Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor.Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lowe...

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Section: Chapter 1 Backgroundmentioning

confidence: 99%

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Pillai¹

2015

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“…Une architecture de CAN à entrelacement temporel hiérarchique ( [86], [87]) est utilisée en raison de son fort potentiel de parallélisme. Afin de surmonter les limites précisées en 1.3.5, seulement quatre échantillonneurs (TH) passifs sont entrelacées.…”

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“…A SAR hierarchical interleaved architecture ( [86], [87]) is used because of its high potential for parallelism. In order to overcome the limitations detailed in 1.3.5, only four passive THs are being interleaved.…”

Section: Adcmentioning

confidence: 99%

Broadband Direct RF Digitization Receivers

Jamin¹

2014

Analog Circuits and Signal Processing

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“…A few other very high speed, time interleaved SAR ADCs were described, e.g. [49][50][51]. This certainly defies the argument that a flash ADC is the fastest analog-to-digital conversion architecture.…”

Section: Single and Multi-bit Adc Architecturesmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

Cited by 64 publications

References 2 publications

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Broadband Direct RF Digitization Receivers

Recent Advances and Trends in High-Performance Embedded Data Converters

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