A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

Doris, Kostas; Janssen, Éric; Nani, Claudio; Zanikopoulos, A.; Weide, G. van der

doi:10.1109/isscc.2011.5746272

Cited by 27 publications

(21 citation statements)

References 3 publications

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“…It has the inevitable zero-crossing error at the right boundary region. To solve those problems, dummy circuits, calibration engine, and other methods have been published [10][11][12][13][14][15][16]. However, they have a few drawbacks of huge power consumption, large chip area.…”

Section: Circuit Description 1 Odd Number Of Folding Blocksmentioning

confidence: 99%

“…Thus it is a great constraint of high resolution ADCs because of its huge power consumption and chip area. To overcome those problems, folding structure has been continuously studied [4][5][6][7][8][9][10][11][12][13][14][15][16]. However, folding ADCs have an asymmetry error at the boundary conditions, since there is even number of folding blocks [5].…”

Section: Introductionmentioning

confidence: 99%

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A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Lee¹,

Lee²,

Song

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm 2 and the power dissipation is about 120 mW.The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

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Section: Circuit Description 1 Odd Number Of Folding Blocksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Lee¹,

Lee²,

Song

2014

JSTS:Journal of Semiconductor Technology and Science

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“…1, including a mixed-signal front-end IC [5] and 4 256QAM demodulators [10]. Bit Error Rate (BER) tests have been conducted demonstrating the reception of 4 independent wanted channels among 157 channels.…”

Section: B System-level Measurementsmentioning

confidence: 99%

“…Specifically, when the wanted channels are reduced with respect to the adjacent channels, referred as Desired over Undesired ratio (D/U), and when a cable tilt is applied as in Fig.2, an ADC sampling at 2.5GHz needs an SNR in excess of 61dB. This is well above current ADC state-of-the-art [4], [5], [6]. This paper describes a robust RF front-end which enables the full cable band reception with a single direct RF sampling receiver.…”

Section: Introductionmentioning

confidence: 97%

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An RF front-end for multi-channel direct RF sampling cable receivers

Jamin¹,

Rambeau²,

Goussin³

et al. 2011

2011 Proceedings of the ESSCIRC (ESSCIRC)

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This paper presents a broadband fully integrated high dynamic range RF front-end with a single-inductor programmable RF amplitude equalizer, 45dB variable gain range, 4.5dB NF, 60dB CSO/CTB, and 25dB anti-aliasing protection. It is designed in a 40GHz-ft BiCMOS 0.25µm process, consumes 400mW from a 3.3V supply, and enables a cable full-spectrum receiver to capture >16 channels over an 50MHz-1GHz RF band.

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Recent progress on CMOS successive approximation ADCs

Matsuura

2016

IEEJ Transactions Elec Engng

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Recent progress in CMOS integrated successive approximation (SAR) analog-to-digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non-necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time-interleaved architecture, it achieves a very high speed conversion rate of 90 G-sample/s with an 8-bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10-bit, 200 k-sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR-ADC circuit techniques and the achieved performances.

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A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

Cited by 27 publications

References 3 publications

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

An RF front-end for multi-channel direct RF sampling cable receivers

Recent progress on CMOS successive approximation ADCs

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