Epitaxial growth of stoichiometric SiC on Si(111) and 2°–5° off-oriented 6H–SiC(0001) substrates was carried out at low temperatures (800–1000 °C) by means of solid-source molecular beam epitaxy controlled by a quadrupole mass spectrometry based flux meter. The films were obtained on Si-stabilized surfaces showing (3×3) and (2×2) superstructures in the case of SiC(0001). The reflection high-energy diffraction (RHEED) patterns and damped RHEED-oscillations during the growth on 6H–SiC(0001) at T≳900 °C indicate that two-dimensional nucleation on terraces is the dominant growth process.
The Si/dielectric interface properties influence device performance significantly. Often the interface is not stable and changes during and/or after the growth. For a better understanding of the interface and layer formation processes of Nd2O3 on Si(001), as an example for the lanthanide oxides, well-defined experimental studies by reflection high-energy diffraction and x-ray photoelectron spectroscopy were performed under ultraclean ultrahigh vacuum conditions of molecular beam epitaxy. Complementary investigations were performed by transmission electron microscopy. We found that Nd2O3 is a candidate for replacing silicon dioxide as gate dielectric in future Si devices with suitable band gap and offset with respect to silicon. However, under ultrahigh vacuum conditions, silicide formation occurs in the initial stage of growth, which can result in large silicide inclusions and hole formation during further growth. This effect can be completely prevented by modifying the oxygen partial pressure during the interface formation and layer growth.
We investigated the influence of additional oxygen supply and temperature during the growth of thin Gd2O3 layers on Si(001) with molecular beam epitaxy. Additional oxygen supply during growth improves the dielectric properties significantly; however, too high oxygen partial pressures lead to an increase in the lower permittivity interfacial layer thickness. The growth temperature mainly influences the dielectric gate stack properties due to changes of the Gd2O3∕Si interface structure. Optimized conditions (600°C and pO2=5×10−7mbar) were found to achieve equivalent oxide thickness values below 1nm accompanied by leakage current densities below 1mA∕cm2 at 1V.
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