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The Si/dielectric interface properties influence device performance significantly. Often the interface is not stable and changes during and/or after the growth. For a better understanding of the interface and layer formation processes of Nd2O3 on Si(001), as an example for the lanthanide oxides, well-defined experimental studies by reflection high-energy diffraction and x-ray photoelectron spectroscopy were performed under ultraclean ultrahigh vacuum conditions of molecular beam epitaxy. Complementary investigations were performed by transmission electron microscopy. We found that Nd2O3 is a candidate for replacing silicon dioxide as gate dielectric in future Si devices with suitable band gap and offset with respect to silicon. However, under ultrahigh vacuum conditions, silicide formation occurs in the initial stage of growth, which can result in large silicide inclusions and hole formation during further growth. This effect can be completely prevented by modifying the oxygen partial pressure during the interface formation and layer growth.

The ability to integrate crystalline metal oxide dielectric barrier layers into silicon structures can open the way for a variety of novel applications which enhances the functionality and flexibility ranging from high‐K replacements in future MOS devices to oxide/silicon/oxide heterostructures for nanoelectronic application in quantum‐effect devices. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. Additional oxygen supply during growth improves the dielectric properties significantly. Experimental results for Gd2O3‐based MOS capacitors grown under optimized conditions show that these layers are excellent candidates for application as very thin high‐K materials replacing SiO2 in future MOS devices. Epitaxial growth of lanthanide oxides on silicon without any interfacial layer has the advantage of enabling defined interfaces engineering. We will show that the electrical properties of epitaxial Gd2O3 thin films on Si substrates can further be improved significantly by an atomic control of interfacial structures. Finally, we will present a new approach for nanostructure formation which is based on solid‐phase epitaxy of the Si quantum‐well combined with simultaneous vapor‐phase epitaxy of the insulator on top of the quantum‐well. Ultra‐thin single‐crystalline Si buried in a single‐crystalline insulator matrix with sharp interfaces was obtained by this approach on Si(111). In addition, structures consisting of a single‐crystalline oxide layer with embedded Si nanoclusters for memory applications will also be demonstrated. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

The recent discovery of ferroelectricity in thin film HfO2 materials renewed the interest in ferroelectric FET (FeFET) as an emerging nonvolatile memory providing a potential high speed and low power Flash alternative. Here, we report more insight into FeFET performance by integrating two types of ferroelectric (FE) materials and varying their properties. By varying the material type [HfO2 (HSO) versus hafnium zirconium oxide (HZO)], optimum content (Si doping/mixture ratio), and film thickness, a material relation to FeFET device physics is concluded. As for the material type, an improved FeFET performance is observed for HZO integration with memory window (MW) comparable to theoretical values. For different Si contents, the HSO based FeFET exhibited a MW trend with different stabilized phases. Similarly, the HZO FeFET shows MW dependence on the Hf:Zr mixture ratio. A maximized MW is obtained with cycle ratios of 16:1 (HfO2:Si) and 1:1 (Hf:Zr) as measured on HSO and HZO based FeFETs, respectively. The thickness variation shows a trend of increasing MW with the increased FE layer thickness confirming early theoretical predictions. The FeFET material aspects and stack physics are discussed with insight into the interplay factors, while optimum FE material parameters are outlined in relation to performance.