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Short, medium, and long on-chip interconnections having linewidths of 0.45-52 m are analyzed in a five-metallayer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

This paper addresses some of the problems encountered in propagating high-speed signals on lossy transmission lines encountered in highperformance computers. A technique is described for including frequency-dependent losses, such as skin effect and dielectric dispersion, in transmission line analyses. The disjoint group of available tools is brought together, and their relevance to the propagation of high-speed pulses in digital circuit applications is explained. Guidelines are given for different interconnection technologies to indicate where the onset of severe dispersion takes place. Experimental structures have been built and tested, and this paper reports on their electrical performance and demonstrates the agreement between measured data and waveforms derived from analysis. The paper

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A review is presented of the electrical characteristics of highdensity, high-performance interconnections used in digital and communication applications. These interconnections behave as lossy transmission lines for the frequency range of interest. A brief theoretical explanation of the key properties of lossy, coupled transmission lines is given. A new short-pulse propagation technique used for characterizing a large category of wiring is described. A detailed description is made of each of the major interconnect types encountered, namely, shielded cables, printed circuit boards, ceramic carriers, thin-film wiring, and on-chip wiring. Representative examples are given in each case to highlight the key performance-limiting parameters. The modeling and measurement techniques used are explained and examples are given. Future technological directions and their effect on performance are discussed.

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