When are transmission-line effects important for on-chip interconnections?

Deutsch, A.; Kopcsay, G.V.; Restle, P.J.; Smith, H.; Katopis, G.A.; Becker, W.D.; Coteus, P.; Surovic, C.W.; Rubin, B.J.; Dunne, Rajiv; Gallo, Tom; Jenkins, K.A.; Terman, Lewis M.; Dennard, R.H.; Sai-Halasz, G.A.; Krauter, B.; Knebel, D.R.

doi:10.1109/22.641781

Cited by 349 publications

(125 citation statements)

References 6 publications

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“…In current technology, the use of low resistance material, faster signal rise time, longer wire length and high switching speed leads to significant value of wire inductance (Ismail & Friedman, 1999). It is more effective to model the interconnect as distributed RLC transmission line rather than single RC (Deutsch et al, 1997). Accurate prediction of propagation delay and coupling noise in interconnects is strongly dependent on the per unit wire and coupling parasitics.…”

Section: Introductionmentioning

confidence: 98%

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Sharma¹,

Kaushik

Sharma

2013

International Journal of Electronics

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This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/ topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

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Section: Introductionmentioning

confidence: 98%

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Sharma¹,

Kaushik

Sharma

2013

International Journal of Electronics

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“…All together, these factors seriously aggravate the inductive coupling between wires in modern designs [4][5][6][7].…”

Section: Introductionmentioning

confidence: 98%

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Soudan

2005

Analog Integr Circ Sig Process

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Recent advances in Deep Submicron (DSM) design and manufacturing technologies have brought to the forefront the importance of inductive coupling amongst long interconnect in high performance microprocessors. Inductive coupling has been shown to depend directly on the overlap length between adjacent signal wires, the activity on these wires and the distance separating them. This paper presents a technique-known as swizzling-that exploits the inductive coupling dependence on distance to reduce the effect of any particular attacker on any of its victims. In the swizzling technique, the order of signal wires in global signal busses is continuously re-arranged to move attackers and victims away from each other. This paper shows that this technique significantly reduces the inductive coupling for the most vulnerable wires neighboring the attacker with zero area and routing resource penalty.

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“…Generally speaking, at low frequencies, i.e., the length of the interconnect lines is electrically small at the frequency of interest, interconnect lines can be modeled using lumped RC (first-order system for monotonic waveform) or RLC (second-order system needed for ringing phenomena) circuit model [2]. To model the interconnect lines more precisely, a large number of lumped sections are often needed, which leads to circuit equations with very large dimension, high CPU intensive and memory exhaustive simulations.…”

Section: Introductionmentioning

confidence: 99%

Analysis of on-chip distributed interconnects based on Pade expansion

Wang

2009

J. Control Theory Appl.

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In this paper, on-chip interconnects are modeled as distributed parameter RLCG transmission lines, based on which the matrix ABCD of interconnects is deduced. With help of the ABCD matrix, a voltage transfer function of an interconnect system, consisting of a driver, interconnect line and load, is obtained analytically in the form of a transcendental function, and it is reduced to a finite order system based on high order Pade approximation. With the reduced-order transfer function, response waveforms with step input can be obtained, and signal delay can be calculated consequently. Two numerical experiments are conducted to demonstrate its efficiency.

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When are transmission-line effects important for on-chip interconnections?

Cited by 349 publications

References 6 publications

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Analysis of on-chip distributed interconnects based on Pade expansion

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