Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Abstract

This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/ topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

“…The voltage and current at discrete points on the line are numerically computed using recursive equations ( 3) and (4). Equations ( 8)- (11) are the recursive relations at source end and load end respectively. The stability of the FDTD technique is determined by the Courant condition, which states that the time step (t ) must not be greater than the propagation time over each cell OE17 .…”

“…The effect of unequal transition time on crosstalk has been reported in Ref. [11]. The study of unequal transition time is important because it is quite common to have mismatching in the rise time of input signals propagating through different length wires.…”

“…The effect of coupling parasitics on signal transition time has been reported in Ref. [11]. Usually authors have analyzed the effect of transition time on performance parameters by taking it as equal for the inputs to interconnect lines.…”