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Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer. The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime. Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations. Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits. It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block. The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits. In this article, ONOFIC approach is compared with the LECTOR leakage reduction technique and output results show that our proposed approach significantly reduces the power dissipation and enhancing the speed of the logic circuits with superior power-delay product.

Quantum‐dot cellular automata (QCA) is a transistor‐less technology to implement the nanoscale circuit designs. QCA circuits are fast, highly dense and dissipate less energy as compared to widely used complementary metal oxide semiconductor (CMOS) technology. In this paper, a novel structure for digital comparator using QCA nanotechnology is proposed. Digital comparator is a basic and important module in central processing unit which compares two binary numbers. The proposed digital comparator is optimal, single layered with 0.50 clock latency and containing only 26 QCA cells. The proposed digital comparator is compared for the different performance metrics with the existing digital comparators. The calculations for energy dissipation are provided using QCA Designer‐E and QCA Pro tools. The proposed coplanar digital comparator is designed with minimum QCA cells which reduces the total cell area, total covered area and cost. Total cell area, total covered area and cost for the proposed digital comparator are 0.008 μm2, 0.023 μm2 and 0.006 respectively. Results show that energy dissipation for the proposed design is very less therefore, proposed digital comparator is energy efficient.

The paper strives to elucidate the complex yet intimate relation between spirituality and mental health from contemporary perspectives. The diverse and constantly evolving views that spiritualists and mental health professionals have held toward each other over last century are discussed with special accent on the transpersonal spiritual framework within psychology. The role of spirituality in promoting mental health and alleviating mental illness is highlighted. The paper is concluded with an increasing need to integrate spirituality within the mental health field albeit there are several impediments in achieving the same, which need to be worked through circumspectly.

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Background: As variability in the clinical profile of dementia subtypes had been reported with regional differences across the world, we conducted a retrospective hospital-based study in a North Indian population. Methods: We retrieved patient records from 2007 to 2014 for details of clinical evaluation, diagnosis, neuroimaging, biochemical investigations, and follow-up of 1,876 patients with dementia (PwD), and the data were analyzed using descriptive statistics. Results: Of the total PwD, Alzheimer disease (AD) accounted for 30% followed by vascular dementia (VaD) 26%, mixed dementia (MD) 21%, Parkinson-related dementia 11%, frontotemporal dementia (FTD) 7%, and infective dementia 5%. Of all PwD excluding the infective group (n = 1,777), 63% were men, 39% were from rural areas, 87% had behavioral abnormalities along with cognitive deficits, and 73% had impaired ADLs. Among dementia subtypes, a positive family history, cardiovascular and metabolic risk factors, and behavioral abnormalities were found to be distributed. However, there existed a predominance of specific behavioral pattern in each subtype. The mean duration of follow-up varied from 2.9 ± 2.3 (VaD) to 3.6 ± 2.1 (AD) and greater than 30% were found to be stable on treatment (except in dementia with Lewy body). Conclusions: This large hospital-based study provides a distribution pattern and clinical spectrum of dementia subtypes in a North Indian population.

Summary Nanotechnology and very large‐scale integration (VLSI) fabrication have a reflective productivity. The growth of one demands the growth of the other. In nanotechnology, quantum‐dot cellular automata (QCA) secures as the best alternative for replacement of complementary metal‐oxide semiconductor (CMOS) technology for integrated circuit (IC) fabrication. This paper presents an integration of the two domains wherein a novel ultraefficient, multioperative 3 × 3 universal reversible gate, Sadat Farah Vijay (SFV)‐QCA, is proposed and implemented in QCA technology using majority voter approach. SFV‐QCA gate is redesigned and restructured using precise QCA cell interaction for optimization. The basic logic gates are implemented using the proposed SFV‐QCA gate to validate its universality. All the 13 standard Boolean functions are implemented using SFV‐QCA to demonstrate its multioperation nature. One‐bit full adder and subtractor circuits are designed using SFV‐QCA gate and compared with the previous works. The analysis of the SFV‐QCA gate shows that it is ultraefficient and more robust as compared to previous works. Energy dissipation analysis of the designs has also been presented, and the investigation establishes minimum energy dissipation of the designs that confirms ultrahigh efficient designs.

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, inputdependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.