PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Sharma, Vibha; Pattanaik, Manisha; Raj, Balwinder

doi:10.1016/j.microrel.2013.09.018

Cited by 44 publications

(10 citation statements)

References 18 publications

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“…The schematic arrangement of the proposed leakage reduction approach is shown in fig. 1 It uses the concepts of ONOFIC approach [6] as well as INDEP approach [12]. ONOFIC block operates as per the logic available at output terminal.…”

Section: Input Dependent Onofic Approachmentioning

confidence: 99%

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A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

2016

6th International Conference on Advances in Engineering Sciences and Applied Mathematics (ICAESAM-2016) Dec. 21-22, 2016 Kuala

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With the rise of the number of electronic portable devices, the importance of leakage power reduction techniques are increasing. Leakage power dissipation has become one of the critical issues in modern integrated circuit. This work focuses on the low power circuit design, which is showing an ever increasing growth with the scaling of technology nodes. Supply voltage and threshold voltage of the device are scaled down to maintain the performance at lower technology nodes. Reduction in threshold voltage causes leakage power in the concerned device. The number of gates per chip has been increasing with technology scaling which resulted in large leakage power dissipation. The demand of low power integrated circuits is increasing to improve the performance of portable systems. In this research paper, a low leakage circuit level approach is proposed in order to overcome the leakage power dissipation. 4:1 multiplexer is designed and simulated at 32nm technology node by using proposed approach and the results are compared with the conventional 4:1 multiplexer circuit.

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Section: Input Dependent Onofic Approachmentioning

confidence: 99%

“…Based on the selective insertion of control point, leakage reduces to 70% of the total leakage with minimum increase in delays and area [11]. Process variations are the important parameters in nanoscaled regime and calculated in circuit level leakage minimization technique INDEP [12].…”

Section: Introductionmentioning

confidence: 99%

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

2016

6th International Conference on Advances in Engineering Sciences and Applied Mathematics (ICAESAM-2016) Dec. 21-22, 2016 Kuala

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“…PVT variations introduce statistical fluctuations in physical properties of the MOS devices which result in degrading the parametric yield and logic characteristics of the logic gates [1]. One effective approach to combat the PVT variations is using bundled data (BD) design [2], where the programmable delay line tracks the delay of the critical path [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Yield modelling and analysis of bundled data and ring‐oscillator based designs

Zhang

Cheng

et al. 2019

IET Computers & Digital Techniques

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Both ring-oscillator based clocks and bundled-data designs mitigate the ill effects of process, voltage, and temperature (PVT) variations. They both rely on delay lines which, when made post-silicon tunable, offer the opportunity to add test margin into the design in which the delay line in shipped products is set slower than that which is successfully tested. By adopting the uniform and per-chip test margin methods to asynchronous designs, this paper mathematically analyzes the resulting yield and shipped product quality loss and compares them to traditional synchronous design, quantifying the potential benefits that arise from the correlation in delay among paths in the delay line and combinational logic.

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“…Leakage current occurs in both active and standby modes of an application. It is more important to control the leakage current during standby mode when circuit is not in a working condition (Sharma, Pattanaik, & Raj, 2014a, 2014b.…”

Section: Introductionmentioning

confidence: 99%

“…VGND voltage of proposed technique in sleep period is more close to V DD voltage since sleep control block has long path to discharge the little charge of VGND rail as compared to other circuits. V DD reduction is an important scheme to reduce the overall power dissipation for devices which operate in sub-threshold region (Sharma et al, 2014b). Figure 8 illustrates the effect of V DD voltage on low level output voltage of GBONOR technique.…”

mentioning

confidence: 99%

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Sharma

Pattanaik

2015

International Journal of Electronics

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Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-V TH sleep transistors between actual and virtual power/ ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-V TH transistors in place of high-V TH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-V TH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations. IntroductionThe current era of dense complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) tends a bright future for modern battery operated portable systems. Very large scale integration (VLSI) designers have emphasised on miniaturisation of the devices to get better speed and space performances. CMOS technology has been scaled down continuously to meet the specifications of chip area reduction, and hence production cost and power requirements. The scaling of power supply voltage (V DD ) and threshold voltage (V TH ) of a MOS device are the critical parameters in order to maintain the performance and switching speed of the device. V DD must be scaled down as per the new technology generation in order to keep power dissipation and power delivery costs under control (Sharma & Pattanaik, 2013). V TH of the devices should be scaled comparatively with the V DD scaling so that logic circuit can preserve the performance of devices. V TH scaling increases leakage current considerably. As leakage current is increasing more rapidly with each new technology generation, it is the most effective part of the total power dissipation. Leakage current minimisation is the dominant field for circuit

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PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Cited by 44 publications

References 18 publications

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

Yield modelling and analysis of bundled data and ring‐oscillator based designs

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

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