Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Deutsch, A.; Kopcsay, G.V.; Rubin, B.J.; Surovic, C.W.; Terman, Lewis M.; Dunne, Rajiv; Gallo, Tom; Dennard, R.H.

doi:10.1147/rd.395.0547

Cited by 165 publications

(66 citation statements)

References 9 publications

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“…As a result, interconnect delay in long global wires is an increasing problem in integrated circuits (IC) relative to delays in transistor switching [1], [2]. In the latest microelectronics technology nodes, interconnect delay has become the limiting factor in determining the speed of digital systems [3].…”

Section: Introductionmentioning

confidence: 99%

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

Bandyopadhyay

Han

Chung

et al. 2011

IEEE Trans. Compon., Packag. Manufact. Technol.

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Section: Introductionmentioning

confidence: 99%

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

Bandyopadhyay

Han

Chung

et al. 2011

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…5(a) shows from circuit simulation with the actual sample clock drive path included in the simulation. 5 The corresponding sampling function is given in Fig. 5(b) and its Fourier spectrum is given in Fig.…”

Section: Samplersmentioning

confidence: 99%

“…Deutsch [5] measures the time-domain response to a step excitation directly through high-frequency probes and a sampling oscilloscope. Line delay is extracted by subtracting out the delay of a short reference line, thereby (theoretically) eliminating the effects of the probes, cables, and pads.…”

Section: Introductionmentioning

confidence: 99%

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms

Shepard

Zheng²

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

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Abstract-High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with "porch steps" and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25-m process. The layout was extracted using Cadence's Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results.

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“…During this step the design is manipulated significantly, which has a strong influence on the interconnect behavior. Although many publications in literature [3] - [7] have been focused on capacitance characterization of on-chip interconnects the impact of fill structures and design manipulations for yield enhancement has not been addressed sufficiently. Even more manipulations may arise in the future influencing parasitics as well, such as layout manipulations to deal with optical proximity effects.…”

Section: Introductionmentioning

confidence: 99%

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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-Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

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Modeling and characterization of long on-chip interconnections for high-performance microprocessors

Cited by 165 publications

References 9 publications

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

On-chip oscilloscopes for noninvasive time-domain measurement of waveforms

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

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