Designing the best clock distribution network

Restle, P.J.; Deutsch, A.

doi:10.1109/vlsic.1998.687985

Cited by 85 publications

(44 citation statements)

References 7 publications

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“…So, instead of logic dictating the clock period in the multiplier, the clock period (determined by flip-flop) determines the amount of logic that can be enclosed between any two adjacent registers. This is given by (3). Since the clock period has to be at least 320ps, compensating for possible clock uncertainties a clock period of 350ps (≈2.86GHz) (T clkw ) was targeted.…”

Section: Multiplermentioning

confidence: 99%

“…Thus the useful portion of clock period available for computation is decreasing. Significant research is being done to counter such uncertainties by design optimization and technology improvements [3], [4]. Considerable effort has been put into studying various clock distribution schemes like the resistance-capacitance matched tree, the grid, the tree network, and the serpentine.…”

Section: Introductionmentioning

confidence: 99%

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Designing pipelined systems with a clock period approaching pipeline register delay

Tatapudi

Delgado-Frias

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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Abstract-A novel mesochronous pipelining scheme is described in this paper. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by stage with the maximum delay. Also, in the proposed scheme the number of pipeline stages and pipeline registers is small and the clock distribution scheme is simpler. An 8× × × ×8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180nm. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350ps (2.86GHz), with fewer pipeline stages and pipeline registers.

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Section: Multiplermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Designing pipelined systems with a clock period approaching pipeline register delay

Tatapudi

Delgado-Frias

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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“…Non-tree clock distribution topologies (e.g., clock meshes) exhibit useful characteristics due to multi-path signal propagation created by routing redundancies [1][2][3][4][5][6][7][8][9][10][11]. These non-tree clock distribution networks are exploited to distribute the global clock signal over an integrated circuit, and exhibit high immunity to process, voltage, and temperature (PVT) variations, while tolerating non-uniform switching and an unbalanced distribution of the clocked elements.…”

Section: Introductionmentioning

confidence: 99%

“…These networks are composed of a large number of mesh nodes and unbalanced loads, making these networks difficult to analyze, optimize, and automate [6], [12], [13]. Routing redundancies require significant resources as compared to optimized tree-based clock distribution networks where point-topoint routing is used [7]. Meshes dissipate higher power [12] due to the large capacitance incurred by the additional metal wires and drivers.…”

Section: Introductionmentioning

confidence: 99%

Timing-driven variation-aware nonuniform clock mesh synthesis

Abdelhadi

Ginosar

Kolodny

et al. 2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maximum skew.

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“…Clock gating [11] is a widely used technique to reduce power dissipation. To achieve lower skew between two sequentially-adjacent registers, the clock network is often designed as a symmetric structure, such as an H-tree [12]. Different aspects of the clock distribution network are summarized in [13].…”

Section: Introductionmentioning

confidence: 99%

Globally integrated power and clock distribution network

Jakushokas

Friedman

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-The global networks within a conventional integrated circuits (IC) consists of three major types: power, ground, and clock networks. These three networks consumes most of the metal resources in the highest metal layers. The signals traversing the power and clock distribution networks are fundamentally different in terms of signal frequency and current flow. Combining the power and clock network into a globally integrated network is therefore possible. In this paper, the general concept of a globally integrated power and clock (GIPAC) system is proposed. The circuitry supporting this GIPAC system is also presented. Simulation results based on a 90 nm CMOS technology demonstrate the potential of GIPAC.

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Designing the best clock distribution network

Cited by 85 publications

References 7 publications

Designing pipelined systems with a clock period approaching pipeline register delay

Designing pipelined systems with a clock period approaching pipeline register delay

Timing-driven variation-aware nonuniform clock mesh synthesis

Globally integrated power and clock distribution network

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