Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Abstract

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Silicon carrier for computer systems

“…To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Several papers have been published recently by IBM research that introduced the silicon carrier technology for a wide range of twoand three-dimensional product applications and presented detailed descriptions of its key technology enablers [2,5,7,15,16,22]. In its most basic form, the silicon carrier is a silicon substrate that has fine pitch I/Os and high speed wiring on one side, a typical C4 solder bump on the other side and through-vias that connect the two sides (see Figure 1).…”

“…Such close proximity can significantly enhance the effectiveness of the passives in improving chip performance. For example, silicon carriers with decoupling trench capacitors having the capacitance of 2.5-2.7 μF/cm 2 have been designed and characterized [7]. This high density of capacitance and its close proximity can provide low inductance decoupling for high performance chips.…”

“…It is clear that unconventional methods that focus beyond the scaling of the CMOS devices have to be employed in order to sustain the performance growth of computer systems. At the system and packaging level, one such method involves use of silicon carrier technology which is capable of providing high I/O density, high speed signaling and efficient power distribution system [7,15]. By supporting signal wiring pitch of less than 2 μm, I/O density pitch of less than 50 μm, chip proximity of less than 100 μm and host of embedded passive devices as well as integration of heterogeneous technologies, the silicon carrier bridges a wide gap that always existed between the chip and the package and in turn, transforms performance limiting packaging bottlenecks into opportunities that system architects and designers can exploit to sustain the historic performance of computer systems.…”

Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

“…1,2 For example, the currently available IC (integrated circuit) chips used in wearable electronic system are built on silicon wafers of thickness less than 100µm. And the inorganic chips used in flexible electronic system [3][4][5][6][7][8] should be thinned to micro-membranes of thickness about 15µm to improve the mechanical flexibility of devices to adapt to arbitrary curved objects.…”

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

“…Fig. 1 depicts interconnect scaling trend as integration technology evolves from system on printed-circuit-board (PCB) [5] through system-in-a-package (SiP) to systemon-a-chip (SoC) [6]. Distances between modules and thus the lengths of wires shrink as integration density increases.…”