On-chip wiring design challenges for gigahertz operation

Deutsch, A.; Coteus, P.; Kopcsay, G.V.; Smith, H.; Surovic, C.W.; Krauter, B.; Edelstein, D.; Restle, P.L.

doi:10.1109/5.920582

Cited by 180 publications

(85 citation statements)

References 51 publications

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“…For the application of transmission lines as global interconnect in CMOS circuits, electromagnetic (full-wave and quasi-TEM) analyses of on-chip transmission lines on silicon substrate (e.g., [18], [20], [26], [27], [29]) provided the groundwork. Circuit-level studies (e.g., [16], [17], [21], [34]) have been carried out to characterize the performance of transmission line based onchip interconnect. Novel signaling and modulation schemes have been proposed [14], [25].…”

Section: Background and Related Workmentioning

confidence: 99%

A design space exploration of transmission-line links for on-chip interconnect

Carpenter¹,

Hu$^{²,

Huang³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient. Well-engineered transmission linebased communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level analyses and tradeoffs. This paper makes a first-step effort in exploring part of the design space. Using detailed simulation-based analysis, we show that a shared-medium fabric based on transmission line can offer better performance and a much better energy profile than a conventional mesh interconnect.

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Section: Background and Related Workmentioning

confidence: 99%

A design space exploration of transmission-line links for on-chip interconnect

Carpenter¹,

Hu$^{²,

Huang³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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“…The scheme without adding termination resistance is shown in Figure 1(a), which follows the structure in the work [7] and [16]. For identification, we refer this scheme as T-line Scheme A.…”

Section: A Interconnect Schemes Using T-linesmentioning

confidence: 99%

“…It has been shown in [7] that, under some conditions, transmission line effects need to be considered for on-chip wires. If the wires are operated in LC-region, the wire delay will be determined by the wave propagation delay, which is much smaller than the wire RC delay.…”

Section: Introductionmentioning

confidence: 99%

“…The first scheme adopts tapered inverter chain (equal sizeprogressive ratio) as the driver and receiver of long global wire, which is based on the work of [7] and [16]. By choosing larger wire geometry and proper driver impedance, this scheme could achieve better performance compared with repeated RC wires in terms of total delay and Far-End Noise (FEN).…”

Section: Introductionmentioning

confidence: 99%

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Design methodology of high performance on-chip global interconnect using terminated transmission-line

Zhang

Deutsch

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-We explore two schemes using transmissionline (T-line) to achieve high-performance global interconnects on VLSI chips. For both schemes, we select wire dimensions to ensure T-line effects present and employ inverter chains as drivers and receivers. In order to achieve high throughput and alleviate Inter-Symbol Interference (ISI), high termination resistance is used in the second scheme. For the two schemes, we discuss how to optimize the wire dimensions and the effects of driver impedance and termination resistance on the wire bandwidth. Secondly, design methodology is proposed to determine the optimal design variables for three objectives. We adopt the proposed methodology and compare the performance metrics with repeated RC wires. Simulation results show that, the proposed T-line schemes reduce the delay and improve the throughput as much as 82% and 63%, for min-ddp (delay 2 -power product) objective.

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“…This implies that transmission-line properties must be accounted for. It was shown in [4] that any two uniform parallel conductors, the signal and the current return path, that are used to transmit electromagnetic energy can be considered transmission lines. The current return path can be a ground plane, a ground conductor, or a mesh of ground lines on many layers.…”

Section: Transmission Linementioning

confidence: 99%