Using ILA testing for BIST in FPGAs

Stroud, Charles E.; Lee, E.; Konala, S.; Abramovici, M.

doi:10.1109/test.1996.556946

Cited by 44 publications

(20 citation statements)

References 19 publications

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“…Logic blocks and embedded blocks inside an FPGA are usually connected through these interconnections including programmable switches and buffers which make these separate blocks work together properly. It is rather challenging as well as necessary to test all the interconnect resources in an FPGA [4,5,6,7,8,9,10]. Interconnect resources include line segments and programmable interconnect points (PIPs).…”

Section: Introductionmentioning

confidence: 99%

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A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Yang

Liang

Wang

et al. 2015

IEICE Electron. Express

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Testing of interconnect resources is one of the most important parts in FPGA testing, since most of the transistors in the chip are dedicated to interconnections. Conventional testing methods are no longer as efficient as before because of the various new types of interconnections and a lack of enough input output blocks (IOBs) in the FPGAs that are based on general routing matrix (GRM). This paper presents a new automatic method for testing FPGA interconnect resources in GRM-based FPGAs. This new method, testing line segments and programmable interconnect points (PIPs) in different stages, is applicable to all kinds of GRM-based FPGAs. Experimental results show that a total of 152 test configurations are sufficient to achieve 99.2% and 99.7% fault coverage for line segments and PIPs in Xilinx XC4VLX15 FPGA respectively and to largely reduce the number of IOBs required in the testing.

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Section: Introductionmentioning

confidence: 99%

“…Another way to detect faults in FPGA interconnections is based on iterative logic arrays (ILAs), which repeatedly reconfigures the FPGA as a group of testable ILAs [10]. In this way, test configurations can be reduced due to the regularity of the FPGA structure.…”

Section: Introductionmentioning

confidence: 99%

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Yang

Liang

Wang

et al. 2015

IEICE Electron. Express

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“…Sometimes separate ILAs are used to propagate errors from the logic under test [39][40] [20]. Constructing ILAs to test the RAM operation of PLBs is described in [39] [18][32] [33].…”

Section: Introductionmentioning

confidence: 99%

BIST-based test and diagnosis of FPGA logic blocks

Abramovici¹,

Stroud

2001

IEEE Trans. VLSI Syst.

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100

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We present a Built-In Self-Test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers, that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

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“…This is a lot less than that needed by any configurationindependent testing method providing equal fault coverage. Note that this method can be implemented as a self-test and compared to the self-test approach of [8] [9] it requires fewer test sessions and yet provides complete fault coverage for both the CLBs and the interconnects.…”

Section: Resultsmentioning

confidence: 99%

Configuration self-test in FPGA-based reconfigurable systems

Quddus

Jas²,

Touba

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for rapidly testing the configuration in the FPGAs each time the system is reconfigured. A low-cost configuration-dependent test method is used to detect faults in the circuit. The "original configuration" is modified by only changing the logic function of the CLBs to form "test configurations" that can be used to quickly test the circuit. The test procedure is rapid enough to be performed on the fly whenever the system is reconfigured. The technique is independent of any fault model since it partitions the circuit into segments and tests each segment exhaustively.

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Using ILA testing for BIST in FPGAs

Cited by 44 publications

References 19 publications

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

BIST-based test and diagnosis of FPGA logic blocks

Configuration self-test in FPGA-based reconfigurable systems

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