A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Abstract

Testing of interconnect resources is one of the most important parts in FPGA testing, since most of the transistors in the chip are dedicated to interconnections. Conventional testing methods are no longer as efficient as before because of the various new types of interconnections and a lack of enough input output blocks (IOBs) in the FPGAs that are based on general routing matrix (GRM). This paper presents a new automatic method for testing FPGA interconnect resources in GRM-based FPGAs. This new method, testing line segments and programmable interconnect points (PIPs) in different stages, is applicable to all kinds of GRM-based FPGAs. Experimental results show that a total of 152 test configurations are sufficient to achieve 99.2% and 99.7% fault coverage for line segments and PIPs in Xilinx XC4VLX15 FPGA respectively and to largely reduce the number of IOBs required in the testing.

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

“…The ADT of interconnect resources attempt to cover all given types of faults on nets, the signal paths constructed from multiple interconnect resources [4,5,19,20,21,22], rather than test each resource individually. Test strategies are categorized into three major types, including coding-based algorithms [2,8,14,15,16,21], SAT/SMT-based algorithms [3,9,17], and ATPG-related approaches [6,9,11,23,24].…”

“…Field programmable gate array (FPGA) is a programmable device that consists of high density and well-organized logic units and programmable interconnect resources [1,2,3,4,5]. Modern FPGAs manufactured with latest process can contain over fifty billion transistors, and thus, faults within FPGAs are highly probable [1,4,5,6,7].…”

“…Field programmable gate array (FPGA) is a programmable device that consists of high density and well-organized logic units and programmable interconnect resources [1,2,3,4,5]. Modern FPGAs manufactured with latest process can contain over fifty billion transistors, and thus, faults within FPGAs are highly probable [1,4,5,6,7]. Application-dependent test (ADT) method is an exclusive test method for FPGAs that requires a routed user design as the circuit under test (CUT) [2,3,4,6,8,9,10,11].…”

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

“…The configuration bits of the routing resources usually account for more than 80% of the total configuration memory bits of the island-style FPGA. Furthermore, this number goes up to 90% in some modern FPGAs, and the area of the routing resources covers more than that of the logic resources [4].…”

State synchronization technique based on present input and healthy state for repairable TMR systems

“…Nowadays, embodied systems are used more and more widely in applications such as networks, spaceborne electronic systems, storage systems and process control systems. In particular, the systems based on field programmable gate arrays (FPGAs) have gained a steadily increasing interest in those applications because of their high performance, low nonrefundable-engineering and fast time-to-market [1]. However, such systems often have both timing constraints and fault tolerance requirements.…”