Evolvable hardware (EHW) based on field-programmable gate arrays (FPGAs) opens up new possibilities towards building efficient adaptive system. State of the art EHW systems based on virtual reconfiguration and dynamic partial reconfiguration (DPR) both have their limitations. The former has a huge area overhead and circuit delay, and the later has slow configuration speed and low flexibility. Therefore a general low-cost fast hybrid reconfiguration architecture is proposed in this paper, which merges the high flexibility of virtual reconfiguration and the low resource cost of DPR. Moreover, the bitstream relocation technology is introduced to save the bitstream storage space, and the discrepancy configuration technology is adopted to reduce reconfiguration time. And an embedded RAM core is adopted to store bitstreams which accelerate the reconfiguration speed further. The proposed architecture is evaluated by the online evolution of digital image filter implemented on the Xilinx Virtex-6 FPGA development board ML605. And the experimental results show that our system has lower resource overhead, higher operating frequency, faster reconfiguration speed and less bitstream storage space in comparison with the previous works.
We present a real-time state synchronization approach, called PIHS3TMR here, for the improvement of the real-time performance of the repairable triple modular redundancy systems. In our approach, the repaired module's state synchronization with the other modules is performed by constructing its state directly according to the present input of the system and the present states of the fault-free modules. Experimental results show that, with very small hardware resource overhead and maximum frequency decline, the proposed approach can obtain state synchronization in one clock cycle, which is hundreds of times faster than state-of-the-art state restoration techniques for a Lion2 CPU. And there is no interruption or delay in system functionality during the synchronization process.
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