Structure and Online Self-Repair Mechanisms for Digital Systems Based on System-on-Programmable-Chip

Yao, Rui; Du, Junjie; Zhu, Ping; Wang, Meiqun

doi:10.2514/1.i010594

Cited by 2 publications

(4 citation statements)

References 8 publications

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“…The run time increases with nodes and with random atmospheric conditions. In future, it is planned to use a high performance computing platform to exercise the full potential of the framework with maximum nodes and random environment conditions to realise self-healing electronics architecture 21 . Figure 6.…”

Section: Discussionmentioning

confidence: 99%

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

Balasubramanian

Moorthi

2020

Def. Sc. Jl.

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Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

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Section: Discussionmentioning

confidence: 99%

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

Balasubramanian

Moorthi

2020

Def. Sc. Jl.

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“…E.g., the LUT of 5/6/7 series FPGA has 6 inputs, whose configuration content has 2 6 = 64 bits in total, i.e., 4 16bit half-words. Therefore, a 4*16 character array 𝑐 𝑓 [] [] is adopted to describe its configuration content, the value of 𝑐 𝑓 [𝑘] [𝑖𝑙] can be determined by (5).…”

Section: Modeling Lut Resource 1) Modeling Location Of Lut Resourcementioning

confidence: 99%

“…Step3: Calculate k and il bit-by-bit according to ( 6)-( 7), and obtain the value of 𝑐 𝑓 [𝑘] [𝑖𝑙] according to (5) Step2: Calculate Colofs and introfs for each routing path. Assume that the source and sink CLB coordinates are (srcrow, srccol) and (sinkrow, sinkcol), then the column offset Colofs for L1/L2/L3 can be calculated by (11); and the intra-frame offset introfs for them can be calculated by ( 12) and ( 13), respectively, where CPRR represents the number of CLBs in the minimum RR.…”

Section: Chromosome Decoding and Cb Online Generationmentioning

confidence: 99%

“…The emergence of evolvable hardware (EHW) [1] provides possibilities towards building such systems. EHW has the potential to change its architecture and behavior dynamically and autonomously [2,3,4,5]. In recent years, field programmable gate arrays (FPGAs) based on static random access memory (SRAM) have become the ideal hardware platforms for EHW [6,7].…”

Section: Introductionmentioning

confidence: 99%

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Efficient design methodology for adaptive system based on direct bitstream evolution

Yao

Liang

Qian

et al. 2023

IEICE Electron. Express

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An efficient design methodology for adaptive system based on direct configuration bitstream (CB) evolution has been proposed, which models the relationship between resources and CBs of the field programmable gate array (FPGA), and then generates CBs online according to the models built. The system framework and design methodology have been given and verified on Xilinx Virtex-5 FPGA. Results show that it can implement embedded online self-programming of FPGA's logic and routing resources via modifying CBs directly; and has lower resources overhead, lesser time consumption, and stronger adaptability than the mainstream evolution approaches.

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Structure and Online Self-Repair Mechanisms for Digital Systems Based on System-on-Programmable-Chip

Cited by 2 publications

References 8 publications

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

An Approach to Emulate and Validate the Effects of Single Event Upsets using the PREDICT FUTRE Hardware Integrated Framework

Efficient design methodology for adaptive system based on direct bitstream evolution

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