Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

Zhang, Fan; Guo, Chenguang; Zhang, Shifeng; Chen, Lei; Li, Xuewu; Sun, Hong-xiang; Meng, Yufeng; Chen, Qiliang

doi:10.3390/electronics9122177

Cited by 4 publications

(4 citation statements)

References 19 publications

(31 reference statements)

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“…It does not need to observe the direction of the path in each switch matrix in advance or plan the wiring according to the usual laws. Table 3 shows the comparison results for the wiring of the sextuple line using the theory used in [9,18]. Due to the vast and complex nature of FPGA interconnect resources, multiple path searches and configurations are required to achieve high coverage.…”

Section: Discussionmentioning

confidence: 99%

“…Table 1 pr s used in this paper along with their respective explanations. FPGAs are composed primarily of modules, such as configurable logic blocks (CLBs), input-output blocks (IOBs), interconnect resources (IRs), and block random access memory (BRAM) [9,10]. The CLB is the core resource of the entire FPGA, consisting mainly of programmable resources, such as look-up tables (LUTs), multiplexers, carry chains, and flip-flops, to implement different logical functions.…”

Section: Introductionmentioning

confidence: 99%

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Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Xie

Qi²,

Lin

et al. 2023

Applied Sciences

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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Xie

Qi²,

Lin

et al. 2023

Applied Sciences

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“…As follows from ( 17) and ( 18), there are 9 LUTs in the circuit of BlockS1. The LUT count is determined by the number of equations in (17) and (18). From SBFs (19) and (20) follows that there are 6 LUTs in the circuit of BlockS2.…”

Section: Example Of Synthesismentioning

confidence: 99%

“…The method is aimed at Mealy FSMs implemented with field programmable gate arrays (FPGAs) [13][14][15]. Now, FPGAs are widely used for implementing various digital systems [16][17][18]. Due to this, we chose the FPGA-based Mealy FSMs as a research object.…”

Section: Introductionmentioning

confidence: 99%

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

et al. 2021

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Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

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Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Nirmalraj

Radhakrishnan

Pandiyan

2021

IET Computers & Digital Tech

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Fault detection and diagnosis of a Field-Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck-at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair-wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS'89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is log 2where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by log 2 ðn þ 2Þ when compared with previously published methods available in the literature.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

Cited by 4 publications

References 19 publications

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

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