Configuration self-test in FPGA-based reconfigurable systems

Quddus, W.; Jas, A.; Touba, N.A.

doi:10.1109/iscas.1999.777814

Cited by 28 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If a compactor with more than one output is used and logic block outputs are selectively connected to the compactor outputs (through the network of XOR gates), the failing pattern at the outputs of the compactor can identify failing logic block(s). Test patterns generators (TPGs), such as LFSR, and Output Response Analyzers (ORAs) have been used in the context of FPGA BIST [17,18,19,20,21]. However, the use of parity/checksum precomputation (which requires only one LUT/block rather than a full XOR-tree) and response comparator which uniquely codes the failing block(s), particularly in the context of application-dependent diagnosis, is novel.…”

Section: Configuration Logic Block Detectionmentioning

confidence: 99%

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

Kumar¹

2019

AJECE

View full text Add to dashboard Cite

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

show abstract

Section: Configuration Logic Block Detectionmentioning

confidence: 99%

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

Kumar¹

2019

AJECE

View full text Add to dashboard Cite

show abstract

“…An extensive literature is available for fault detection of interconnects; these approaches can be initially differentiated as application-independent [11][12][13][14][15][16][17][18][19] and application-dependent [2,5,6,8,[20][21][22]. Independent of the type of testing approaches, they strive for a complete (100%) fault coverage with reduced number of test configurations (rather than the number of applied test vectors) that the FPGA must undertake for testing, because it is well known that the number of configurations is the dominant figure of merit for test complexity of FPGAs.…”

Section: Review and Preliminariesmentioning

confidence: 99%

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

Kumar

Almurib

Lombardi

2013

IET Computers & Digital Techniques

View full text Add to dashboard Cite

This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.

show abstract

“…Some techniques for testing FPGAs can be found in Refs. [2,3]. Here, we focus on the testing of unprogrammed FPGAs, for which many research results have been proposed [4 -18].…”

Section: Introductionmentioning

confidence: 99%

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Yeh

Shih

2001

VLSI Design

View full text Add to dashboard Cite

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

show abstract

Configuration self-test in FPGA-based reconfigurable systems

Cited by 28 publications

References 12 publications

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Contact Info

Product

Resources

About