Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Abstract

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations

“…For the remainder of this section, we assume that fault diagnosis techniques have been applied on the FPGA [16,17,18] and the fault map is available.…”

“…In order to detect the faulty SRAMs within the configuration memory, several techniques based on readback feature and dynamic reconfiguration of FPGAs [14,15] have been developed in industry as well as academia. The diagnosis developed in [16,17,18] can be applied to obtain the fault map of the configuration SRAMs. In this paper, we assume that a single error in the configuration bits in a CLB will cause the entire CLB to become erroneous.…”

JHDL Implementation of a BIST Scheme for Testing the Look-Up Tables of SRAM Based FPGAs

“…The regular and symmetric structure of an FPGA makes it ideal for testing using the BIST approach. Numerous BIST methodologies for testing FPGAs have been proposed in the past [1][2][3], [5][6], [8][9][10][11], [15][16][17]. Conventional BIST techniques employ a Test Pattern Generator (TPG) which feeds a test input to the Circuit Under Test (CUT).…”

Fault tolerant placement and defect reconfiguration for nano-FPGAs

“…This algorithm is inspired by the ripple move placement legalization procedure in Mongrel [18]. Here each fault is reconfigured by performing a sequence of node moves originating at the CLB with a faulty BLE and terminating at a CLB with a spare BLE, effectively rippling fault nodes to spare BLEs.…”

“…with spares, requiring re-routing of the fault node connections only, to achieve fast reconfiguration with low timing degradation. We also present a reconfiguration algorithm inspired by the ripple move placement legalization algorithm in Mongrel [18]. Here the faulty elements are reconfigured through a sequence of moves from the fault node to a neighboring spare resource, effectively rippling the faults to spare logic elements.…”