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Abstract-This paper presents a compression/decompression scheme based on selective Huffman coding for reducing the amount of test data that must be stored on a tester and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. In the proposed scheme, the test vectors for the SOC are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the cores. A small amount of on-chip circuitry is used to decompress the test vectors. Given the set of test vectors for a core, a modified Huffman code is carefully selected so that it satisfies certain properties. These properties guarantee that the codewords can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) that requires very small area. Results indicate that the proposed scheme can provide test data compression nearly equal to that of an optimum Huffman code with much less area overhead for the decoder.

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A new form of LFSR reseeding that provides higher encoding eficiency and hence greater reduction in test data storage requirements is described. Previous forms of LFSR reseeding have been static (i.e., test generation is stopped and the seed is loaded at one time) and have required full reseeding (i.e,, n=r bits are used for an r-bit LFSR). The new form of LFSR reseeding proposed here is dynamic (i.e., the seed is incrementally modified while test generation proceeds) and allows partial reseeding (i.e. n e bits can be used). Full static forms of LFSR reseeding are shown to be a special case of the new partial dynamic form of LFSR reseeding. In addition to providing better encoding efficiency, partial dynamic LFSR reseeding has a simpler hardware implementation than previous schemes based on multiple-polynomial LFSRs, and can generate each test vector in fewer clock cycles. Experimental results demonstrate the advantages of the new partial dynamic LFSR reseeding approach.

A novel design-for-test (DFT) technique is presented for designing a core with a "virtual scan chain" which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a normal scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a normal scan chain. The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data and fewer scan shift cycles. The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator. It is done by using LFSRs to "expand" the shorter virtual test vector into a full test vector. Results indicate that virtual scan chains can be designed which are several times shorter than the real scan chains inside the core.

This paper presents a new test resource partitioning scheme that is a hybrid approach between extemal testing and BIST. It reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional extemal testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. The proposed approach is based on weighted pseudo-random testing and uses a novel approach for compressing and storing the weight sets.

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