Using an embedded processor for efficient deterministic testing of systems-on-a-chip

Jas, A.; Touba, N.A.

doi:10.1109/iccd.1999.808576

Cited by 45 publications

(35 citation statements)

References 16 publications

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“…Test data compression has been proposed to reduce the ATE memory requirements at IC test [2] [3] [4]. A disadvantage of test data compression for in-field test is the need of an ATE and the low diagnostic capability.…”

mentioning

confidence: 99%

Efficient Embedding of Deterministic Test Data

Majeed

Ahlström

Ingelsson

et al. 2010

2010 19th IEEE Asian Test Symposium

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Abstract-Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor technologies require not only manufacturing test, but also in-field test. Preferably, the same test set is utilized both at manufacturing test and in-field test. While deterministic test patterns provide high fault coverage, storing complete test vectors leads to huge memory requirements and inflexibility in applying tests. In an IEEE 1149.1 (Boundary scan) environment, this paper presents an approach to efficiently embed deterministic test patterns in the system by taking structural information of the system into account. Instead of storing complete test vectors, the approach stores only commands and component-specific test sets per each unique component. Given a command, test vectors are created by a test controller during test application. The approach is validated on hardware and experiments on ITC'02 benchmarks and industrial circuits show that the memory requirement for storing the test data for a system is highly related to the number of unique components.

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mentioning

confidence: 99%

Efficient Embedding of Deterministic Test Data

Majeed

Ahlström

Ingelsson

et al. 2010

2010 19th IEEE Asian Test Symposium

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“…This paper presents a novel approach for using an embedded processor to aid in deterministic testing of the other components of the SOC (preliminary results were published in [17]). The basic idea is that the tester loads a program along with compressed test data into the processor's on-chip memory.…”

Section: Introductionmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

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“…Although this technique has less compression ratio than Huffman coding, the hardware implementation of the decoder is simpler. Another technique was proposed in [7] which performs decompression of test data based on an embedded processor. The technique is based on storing the differing bits between two test vectors.…”

Section: Core1mentioning

confidence: 99%

A geometric-primitives-based compression scheme for testing systems-on-a-chip

Zahir¹,

Khan²

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

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The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efficient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest ISCAS85 and full-scanned versions of ISCAS89 benchmark circuits. In this paper, itis assumed that an embedded core will be used to execute the decompression algorithm and decompress the test data.

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Using an embedded processor for efficient deterministic testing of systems-on-a-chip

Cited by 45 publications

References 16 publications

Efficient Embedding of Deterministic Test Data

Efficient Embedding of Deterministic Test Data

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A geometric-primitives-based compression scheme for testing systems-on-a-chip

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