Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Abstract

Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

An Architecture for Combined Test Data Compression and Abort-on-Fail Test

“…For example, Chandra and Chakrabarty use FDR (Frequency-Directed Run-Length) code [3] and Gonciari and Al-Hashimi [4] use Huffman-coding. Balakrishnan and Touba [5] use matrix operations, and Jas and Touba [6] use an embedded processor for decompression.…”

Deterministic Test Vector Compression / Decompression Using an Embedded Processor

“…The methods proposed in [10][11][12][13] take advantage of the presence of don't care bits in order to achieve significant compression ratios. Another approach of reducing the amount of test data that needs to be transferred to the SoC is by using the processing power already present in most of the contemporary systems [14][15][16][17][18][19]. Some techniques have been proposed for testing embedded memories [14,15].…”

Matrix-based software test data decompression for systems-on-a-chip

“…However, these techniques are not suited for on-chip decompression since the decompression process is complex and time consuming. Decompression schemes that can be implemented using an embedded processor have been proposed in [11,13]. In [13], encoding is done on optimally reordered test vectors based on geometric shapes.…”

“…The software decompression algorithm required to get back the original test vectors by this method is very complex and is a limitation of the approach. In [11], each test vector is divided into blocks and only those blocks that are different from the preceding vector are stored. Test vectors are then constructed on the fly by a program running on the embedded processor and sent to the appropriate core.…”

“…If test application time is critical, MSD is a better alternative. In Table 8, the compression results for the proposed scheme are compared with the geometric primitives based compression technique described in [13] and the difference vectors based compression described in [11]. As seen from the table, the compression obtained by the proposed scheme is higher than both of the earlier methods for almost all of the circuits.…”